- References
- External links
Standard Delay Format (SDF) is an IEEE standard for the representation and interpretation of timing data for use at any stage of an electronic design process. It finds wide applicability in design flows, and forms an efficient bridge between Dynamic timing verification and Static timing analysisIt was originally developed as an OVI standard, and later modified into the IEEE format. Technically only the SDF version 4.0 onwards are IEEE formats. It is an ASCII format that is represented in a tool and language independent way and includes path delays, timing constraint values, interconnect delays and high level technology parameters. It has usually two sections: one for interconnect delays and the other for cell delays. SDF format can be used for back-annotation as well as forward-annotation. See also: VITAL, EDIF References- {{Cite book| title = 1497-2001 – IEEE Standard for Standard Delay Format (SDF) for the Electronic Design Process| doi = 10.1109/IEEESTD.2001.93359| year = 2001| isbn = 0-7381-3074-5}}
- IEC 61523-3:2004 {{Cite book| title = 61523-3-2004 – IEC/IEEE Delay and Power Calculation Standards - Part 3: Standard Delay Format (SDF) for the Electronic Design Process (Adoption of IEEE Std 1497-2001)| doi = 10.1109/IEEESTD.2004.95750| year = 2004| isbn = 2-8318-7493-9}}
External links- https://web.archive.org/web/20130524215112/http://www.eda.org/sdf/
- [https://web.archive.org/web/20131104211358/http://www.eda.org/sdf/sdf_3.0.pdf Standard Delay Format Specification in PDF format, version 3.0 (1995)]
{{IEEE standards}}{{standard-stub}} 3 : EDA file formats|IEEE DASC standards|IEC standards |