“Intel 5-level paging”的意思、由来-开放百科全书

Current x86-64 processors use a four-level page table structure when operating in 64-bit mode.^[4]{{Rp|2806}} A similar situation arose when the 32 bit IA-32 processors used two levels, allowing up to four gigabytes of memory (both virtual and physical). To support more than 4 GB of RAM, an additional mode of address translation called Physical Address Extension (PAE) was defined, involving a third level.^[4] This was enabled by setting a bit in the CR4 register.^[4]{{Rp|2799}} Likewise, the new extension is enabled by setting bit 12 of the CR4 register (known as LA57).^[1]{{Rp|16}} This is only used when the processor is operating in 64 bit mode, and only may be modified when it is not.^[1]{{Rp|16}} If the bit is not set, the processor operates with four paging levels.

The new extensions allow up to 4 PB of physical memory,^[9] compared to the maximum of 256 TB on previous processors.^[5] As adding another page table multiplies the address space by 512, the virtual limit has increased from 256 TB to 128 PB. An extra nine bits of the virtual address index the new table, so while formerly bits 0 through 47 were in use, now bits 0 through 56 are in use.

As with four level paging, the high-order bits of a virtual address that do not participate in address translation must be the same as the most significant implemented bit. With five-level paging enabled, this means that bits 57 through 63 must be copies of bit 56.^[1]{{Rp|17}} Intel has renamed the existing paging system as "4-level paging", which used to be known as IA-32e paging.^[4]{{Rp|2788}}

Implementation

Support for the extension was submitted as a set of patches to the Linux kernel on 8 December 2016.^[6] As was reported on the Linux kernel mailing list, it consisted of extending the Linux memory model to use five levels rather than four.^[7] This is because, although Linux abstracts the details of the page tables, it still depends on having a number of levels in its own representation. When an architecture supports fewer levels, Linux emulates extra levels that do nothing.^[8] A similar change was previously made to extend from three levels to four.^[9]

Drawbacks

Adding another level of indirection makes page table "walks" longer.^[10] A page table walk occurs when either the processor's memory management unit or the memory management code in the operating system navigates the tree of page tables to find the page table entry corresponding to a virtual address.^[11]^[12]{{Rp|2806}} This means that, in the worst case, the processor or the memory manager has to access physical memory six times for a single virtual memory access, rather than five for the previous iteration of x86-64 processors. This results in slightly reduced memory access speed.^[20] In practice this cost is greatly mitigated by caches such as the translation lookaside buffer (TLB).^[13]

Notes

1. ^¹²³{{Cite web|url=https://software.intel.com/sites/default/files/managed/2b/80/5-level_paging_white_paper.pdf|title=5-Level Paging and 5-Level EPT|publisher=Intel Corporation|date=May 2017}}
2. ^{{BDprefix|p=B}}
3. ^{{Cite news|url=https://www.zdnet.com/article/first-linux-4-14-release-adds-very-core-features-arrives-in-time-for-kernels-26th-birthday/|title=First Linux 4.14 release adds "very core" features, arrives in time for kernel's 26th birthday {{!}} ZDNet|last=Tung|first=Liam|work=ZDNet|access-date=2018-04-25|language=en}}
4. ^{{Cite web|url=https://docs.microsoft.com/en-us/previous-versions/windows/hardware/design/dn613969(v=vs.85)|title=Operating Systems and PAE Support - Windows 10 hardware dev|last=Hudek|first=Ted|website=docs.microsoft.com|language=en-us|access-date=2018-04-26}}
5. ^{{cite web|url=http://developer.amd.com/wordpress/media/2012/10/31116.pdf|title=BIOS and Kernel Developer’s Guide (BKDG) For AMD Family 10h Processors|last=|first=|date=|website=|page=24|format=PDF|archive-url=|archive-date=|dead-url=|accessdate=2018-04-26|quote=Physical address space increased to 48 bits.}}
6. ^¹{{Cite web|url=https://www.phoronix.com/scan.php?page=news_item&px=Intel-5-Level-Paging|title=Intel Working On 5-Level Paging To Increase Linux Virtual/Physical Address Space - Phoronix|author=Michael Larabel|date=9 December 2016|website=Phoronix|language=en|access-date=2018-04-26}}
7. ^{{Cite mailing list|url=http://lkml.iu.edu/hypermail/linux/kernel/1612.1/00383.html|title=[RFC, PATCHv1 00/28] 5-level paging|last=Shutemov|first=Kirill A.|mailinglist=Linux kernel mailing list|date=December 8, 2016|access-date=2018-04-26}}
8. ^{{Cite web|url=https://www.kernel.org/doc/gorman/html/understand/understand006.html|title=Page Table Management|website=www.kernel.org|access-date=2018-04-26}}
9. ^{{Cite web|url=https://lwn.net/Articles/106177/|title=Four-level page tables [LWN.net]|date=October 12, 2004|website=lwn.net|access-date=2018-04-26}}
10. ^{{Cite book|url=https://www.worldcat.org/oclc/1032337814|title=MICRO-50 : the 50th Annual IEEE/ACM International Symposium on Microarchitecture : proceedings : October 14-18, 2017, Cambridge, MA|others=Institute of Electrical and Electronics Engineers., IEEE Computer Society., ACM Special Interest Group on Microprogramming,|isbn=9781450349529|location=New York, New York|oclc=1032337814}}
11. ^{{Cite web|url=http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0301h/I1026235.html|title=ARM Information Center|website=infocenter.arm.com|access-date=2018-04-26}}
12. ^¹²³{{Cite book|url=https://software.intel.com/sites/default/files/managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf|title=Intel® 64 and IA-32 Architectures Software Developer’s Manual|last=|first=|publisher=Intel Corporation|year=2018|isbn=|location=|pages=}}
13. ^¹{{Cite web|url=https://courses.cs.washington.edu/courses/cse451/08au/lectures/10-paging_TLBs.pdf|title=CSE 451: Operating Systems: Paging & TLBs|last=Levy|first=Hank|authorlink=Hank Levy (computer scientist)|date=Autumn 2008|website=University of Washington|archive-url=|archive-date=|dead-url=|access-date={{date|2018-04-26}}}}

Technology

Implementation

Drawbacks

Notes

References