请输入您要查询的百科知识:

 

词条 Back end of line
释义

  1. See also

  2. References

  3. Further reading

{{Refimprove|date=January 2009}}

The back end of line (BEOL) is the second portion of IC fabrication where the individual devices (transistors, capacitors, resistors, etc.) get interconnected with wiring on the wafer, the metalization layer. Common metals are copper and aluminum.[1]

BEOL generally begins when the first layer of metal is deposited on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections.

After the last FEOL step, there is a wafer with isolated transistors (without any wires). In BEOL part of fabrication stage contacts (pads), interconnect wires, vias and dielectric structures are formed. For modern IC process, more than 10 metal layers can be added in the BEOL.

Steps of the BEOL:

  1. Silicidation of source and drain regions and the polysilicon region.
  2. Adding a dielectric (first, lower layer is pre-metal dielectric (PMD) – to isolate metal from silicon and polysilicon), CMP processing it
  3. Make holes in PMD, make a contacts in them.
  4. Add metal layer 1
  5. Add a second dielectric, called the inter-metal dielectric (IMD)
  6. Make vias through dielectric to connect lower metal with higher metal. Vias filled by Metal CVD process.
    Repeat steps 4–6 to get all metal layers.
  7. Add final passivation layer to protect the microchip

Before 1998, practically all chips used aluminum for the metal interconnection layers.[2]

The four metals with the highest electrical conductivity are silver with the highest conductivity, then copper, then gold, then aluminum.{{cn|date=October 2016}}

After BEOL there is a "back-end process" (also called post-fab), which is done not in the cleanroom, often by a different company.

It includes wafer test, wafer backgrinding, die separation, die tests, IC packaging and final test.

See also

  • Front end of line
  • Integrated circuit

References

1. ^{{cite book | title = Handbook of Silicon Wafer Cleaning Technology | edition = 2nd | author = Karen A. Reinhardt and Werner Kern | publisher = William Andrew | year = 2008 | isbn = 978-0-8155-1554-8 | page = 202 | url = https://books.google.com/books?id=UPaD8JUCKr0C&pg=PA202 }}
2. ^{{cite web|url=http://www.pctechguide.com/cpu-architecture/copper-interconnect-architecture|title=Copper Interconnect Architecture}}

Further reading

  • {{cite book|title=Silicon VLSI Technology: Fundamentals, Practice, and Modeling|publisher=Prentice Hall|date=2000|ISBN=0-13-085037-3|chapter=Chapter 11: Back End Technology|pages=681–786}}
  • {{cite book|title=CMOS: Circuit Design, Layout, and Simulation|publisher= Wiley-IEEE|date=2010|ISBN=978-0-470-88132-3|url=https://books.google.com/books?hl=en&lr=&id=N0XgLh2d2pkC|chapter=Chapter 7.2.2: CMOS Process Integration: Backend-of-the-line Integration|pages=199–208 [177–79]}}

2 : Electronics manufacturing|Semiconductor device fabrication

随便看

 

开放百科全书收录14589846条英语、德语、日语等多语种百科知识,基本涵盖了大多数领域的百科知识,是一部内容自由、开放的电子版国际百科全书。

 

Copyright © 2023 OENC.NET All Rights Reserved
京ICP备2021023879号 更新时间:2024/9/20 8:35:59