1. Development tools
     AnadigmDesigner®2 EDA Software    DynAMx Design Lab Software    ICE LAB Software  

2. History

3. See also

4. References

5. External links

A field-programmable analog array (FPAA) is an integrated circuit device containing computational analog blocks (CAB)^[1][2] and interconnects between these blocks offering field-programmability. Unlike their digital cousin, the FPGA, the devices tend to be more application driven than general purpose as they may be current mode or voltage mode devices. For voltage mode devices, each block usually contains an operational amplifier in combination with programmable configuration of passive components. The blocks can, for example, act as summers or integrators.

FPAAs usually operate in one of two modes: continuous time and discrete time.

• Discrete-time devices possess a system sample clock. In a switched capacitor design, all blocks sample their input signals with a sample and hold circuit composed of a semiconductor switch and a capacitor. This feeds a programmable op amp section which can be routed to a number of other blocks. This design requires more complex semiconductor construction. An alternative, switched-current design, offers simpler construction and does not require the input capacitor, but can be less accurate, and has lower fan-out - it can drive only one following block. Both discrete-time device types must compensate for switching noise, aliasing at the system sample rate, and sample-rate limited bandwidth, during the design phase.
• Continuous-time devices work more like an array of transistors or op amps which can operate at their full bandwidth. The components are connected in a particular arrangement through a configurable array of switches. During circuit design, the switch matrix's parasitic inductance, capacitance and noise contributions must be taken into account.

Currently there are very few manufactures of FPAAs. On-chip resources are still very limited when compared to that of an FPGA. This resource deficit is often cited by researchers as a limiting factor in their research.

Development tools

AnadigmDesigner®2 EDA Software

AnadigmDesigner®2 is the second generation EDA software that enables engineers to design and implement dynamically reconfigurable analog circuits within a matter of minutes. It includes a time domain functional simulator. The software takes the design and translates it into C code so that it can be used within an embedded system.

DynAMx Design Lab Software

DynAMX Design Lab is used to configure and simulate a FPAA chip. It puts an analog environment comparable to an FPGA in the hands of engineers. Engineers can quickly design complex analog functions into a fully qualified chip. The software allows engineers to adjust the configuration on-the-fly. It is specifically designed to be reconfigurable and reprogrammable in real time, whether in the lab, in the field or in production.

ICE LAB Software

This is an open source software developed at Georgia Tech which uses place and route tool for an FPGA developed at UToronto.^[3] It also uses open source scilab and Xcos for interface.^[4]

History

The term FPAA was first used in 1991 by Lee and Gulak.^[5] They put forward the concept of CABs that are connected via a routing network and configured digitally. Subsequently, in 1992^[6] and 1995^[7] they further elaborated the concept with the inclusion of op-amps, capacitors, and resistors. This original chip was manufactured using 1.2 µm CMOS technology and operates in the 20 kHz range at a power consumption of 80 mW.

Pierzchala et al introduced a similar concept named electronically-programmable analog circuit (EPAC).^[8] It featured only a single integrator. However, they proposed a local interconnect architecture in order to try and avoid the bandwidth limitations.

The reconfigurable analog signal processor (RASP) and a second version were introduced in 2002 by Hall et al.^[9][10] Their design incorporated high-level elements such as second order bandpass filters and 4 by 4 vector matrix multipliers into the CABs. Because of its architecture, it is limited to around 100 kHz and the chip itself is not able to support independent reconfiguration.

In 2004 Joachim Becker picked up the parallel connection of OTAs (operational transconductance amplifiers) and proposed its use in a hexagonal local interconnection architecture.^[11] It did not require a routing network and eliminated switching the signal path that enhances the frequency response.

In 2005 Fabian Henrici worked with Joachim Becker to develop a switchable and invertible OTA which doubled the maximum FPAA bandwidth.^[12] This collaboration resulted in the first manufactured FPAA in a 0.13 µm CMOS technology

See also

• Field-programmable RF – Field programmable radio frequency devices
• CPLD: Complex Programmable Logic Device
• PSoC: Programmable System-on-Chip
• NoC: Network on a Chip
• Network architecture

References

• "A Programmable and Configurable Mixed-Mode FPAA SoC" Jennifer Hasler et al., Georgia Tech, January 7, 2016.
• "Analog's Answer to FPGA Opens Field to Masses" Sunny Bains, EE Times, February 21, 2008. Issue 1510.
• "Field programmable analog arrays" Tim Edwards, Johns Hopkins University project, 1999.
• [https://www.imtek.de/professuren/mikroelektronik/forschung/low-power-mixed "Field programmable analog arrays" ] Joachim Becker, et al., University of Freiburg, Department of Microsystems Engineering. Hex FPAA Research Project.

External links

• "Integrated Computational Electronics (ICE) Laboratory" Georgia Institute of Technology Project

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