释义 |
- Through-hole packages
- Surface mount
- Chip carrier
- Pin grid arrays
- Flat packages
- Small outline packages
- Chip-scale packages
- Ball grid array
- Transistor, diode, small-pin-count IC packages
- {{Anchor|PIN-PITCH}}Dimension reference Surface-mount Through-hole
- Package dimensions Dual row Quad rows LGA
- Multi-chip packages
- See also
- References
- External links
Integrated circuits are put into protective packages to allow easy handling and assembly onto printed circuit boards and to protect the devices from damage. A very large number of different types of package exist. Some package types have standardized dimensions and tolerances, and are registered with trade industry associations such as JEDEC and Pro Electron. Other types are proprietary designations that may be made by only one or two manufacturers. Integrated circuit packaging is the last assembly process before testing and shipping devices to customers. Occasionally specially-processed integrated circuit dies are prepared for direct connections to a substrate without an intermediate header or carrier. In flip chip systems the IC is connected by solder bumps to a substrate. In beam-lead technology, the metallized pads that would be used for wire bonding connections in a conventional chip are thickened and extended to allow external connections to the circuit. Assemblies using "bare" chips have additional packaging or filling with epoxy to protect the devices from moisture. Through-hole packages Through-hole technology uses holes drilled through the PCB for mounting the components. The component has leads that are soldered to pads on the PCB to electrically and mechanically connect them to the PCB. Acronym | Full name | Remark |
---|
SIP | Single in-line package | DIP | Dual in-line package | 0.1|in|mm|abbr=on|sigfig=3}} pin spacing, rows {{convert|0.3|in|mm|abbr=on|sigfig=3}} or {{convert|0.6|in|mm|abbr=on|sigfig=4}} apart. | CDIP | Ceramic DIP[1] | CERDIP | Glass-sealed ceramic DIP[1] | QIP | Quadruple in-line package | Like DIP but with staggered (zig-zag) pins.[1] | SKDIP | Skinny DIP | 0.1|in|mm|abbr=on|sigfig=3}} pin spacing, rows {{convert|0.3|in|mm|abbr=on|sigfig=3}} apart.[1] | SDIP | Shrink DIP | 0.07|in|mm|abbr=on|sigfig=3}} pin spacing.[1] | ZIP | Zig-zag in-line package | MDIP | Molded DIP[2] | PDIP | Plastic DIP[1] |
Surface mount Acronym | Full name | Remark |
---|
CCGA | Ceramic column-grid array (CGA)[8] | CGA | Column-grid array[8] | Example | CERPACK | Ceramic package[3] | CQGP[4] | LLP | Lead-less lead-frame package | A package with metric pin distribution (0.5–0.8 mm pitch)[5] | LGA | Land grid array[8] | LTCC | Low-temperature co-fired ceramic[6] | MCM | Multi-chip module[7] | MICRO SMDXT | Micro surface-mount device extended technology[8] | Example |
Chip carrier A chip carrier is a rectangular package with contacts on all four edges. Leaded chip carriers have metal leads wrapped around the edge of the package, in the shape of a letter J. Leadless chip carriers have metal pads on the edges. Chip carrier packages may be made of ceramic or plastic and are usually secured to a printed circuit board by soldering, though sockets can be used for testing. Acronym | Full name | Remark |
---|
BCC | Bump chip carrier[8] | - | CLCC | Ceramic lead-less chip carrier[1] | - | LCC | Lead-less chip carrier[8] | Contacts are recessed vertically. | LCC | Leaded chip carrier[8] | - | LCCC | Leaded ceramic-chip carrier[8] | - | DLCC | Dual lead-less chip carrier (ceramic)[8] | - | PLCC | Plastic leaded chip carrier[1][8] | - |
Pin grid arrays {{main article|Pin grid array}} Acronym | Full name | Remark |
---|
OPGA | Organic pin-grid array | - | FCPGA | Flip-chip pin-grid array[8] | - | PAC | Pin array cartridge[9] | - | PGA | Pin-grid array | Also known as PPGA[1] | CPGA | Ceramic pin-grid array[8] | - |
Flat packages {{main article|Quad Flat Package}} Acronym | Full name | Remark |
---|
- | Flat-pack | Earliest version metal/ceramic packaging with flat leads | CFP | Ceramic flat-pack[8] | - | CQFP | Ceramic quad flat-pack[1][8] | Similar to PQFP | BQFP | Bumpered quad flat-pack[8] | - | DFN | Dual flat-pack | No lead[8] | ETQFP | Exposed thin quad flat-package[10] | - | PQFN | Power quad flat-pack | No-leads, with exposed die-pad[s] for heatsinking[11] | PQFP | Plastic quad flat-package[1][8] | - | LQFP | Low-profile quad flat-package[8] | - | QFN | Quad flat no-leads package | Also called as micro lead frame (MLF).[8][12] | QFP | Quad flat package[1][8] | - | MQFP | Metric quad flat-pack | QFP with metric pin distribution[8] | HVQFN | Heat-sink very-thin quad flat-pack, no-leads | - | SIDEBRAZE[13][14] | date=July 2018}} | date=July 2018}} | TQFP | Thin quad flat-pack[1][8] | - | VQFP | Very-thin quad flat-pack[8] | - | TQFN | Thin quad flat, no-lead | - | VQFN | Very-thin quad flat, no-lead | - | WQFN | Very-very-thin quad flat, no-lead | - | UQFN | Ultra-thin quad flat-pack, no-lead | - | ODFN | Optical dual flat, no-lead | IC packaged in transparent packaging used in optical sensor |
Small outline packages Acronym | Full name | Remark |
---|
SOP | Small-outline package[1] | CSOP | Ceramic small-outline package | HSOP | Thermally-enhanced small-outline package | mini-SOIC | Mini small-outline integrated circuit | MSOP | Mini small-outline package | PSOP | Plastic small-outline package[8] | PSON | Plastic small-outline no-lead package | QSOP | Quarter-size small-outline package | The pin spacing are width of 0.635 mm.[8] | SOIC | Small-outline integrated circuit | Also known as SOIC NARROW and SOIC WIDE | SOJ | Small-outline J-leaded package | SSOP | Shrink small-outline package[8] | TSOP | Thin small-outline package[8] | Example | TSSOP | Thin shrink small-outline package[8] | TVSOP | Thin very-small-outline package[8] | µMAX | Similar to a SOIC. (A Maxim trademark [https://web.archive.org/web/20110714053431/http://datasheets.maxim-ic.com/en/ds/MAX9716-MAX9717.pdf example]) | WSON | Very-very-thin small-outline no-lead package |
Chip-scale packages Acronym | Full name | Remark |
---|
BL | Beam lead technology | Bare silicon chip, an early chip-scale package | CSP | Chip-scale package | Package size is no more than 1.2× the size of the silicon chip[15][57] | TCSP | True chip-size package | Package is same size as silicon[16] | TDSP | True die-size package | Same as TCSP[16] | WCSP | Wafer-level chip-scale package | MICRO SMD | - | Chip-size package (CSP) developed by National Semiconductor[17] | COB | Chip-on-board | Bare silicon chip, that is usually an integrated circuit, is supplied without a package. | COF | Chip-on-flex | Variation of COB, where a chip is mounted directly to a flex circuit. | COG | Chip-on-glass | Variation of COB, where a chip is mounted directly to a piece of glass - typically an LCD. |
Ball grid array {{main article|Ball grid array}}Ball Grid Array BGA uses the underside of the package to place pads with balls of solder in grid pattern as connections to PCB.[1][8] Acronym | Full name | Remark |
---|
FBGA | Fine-pitch ball-grid array | A square or rectangular array of solder balls on one surface[8] | LBGA | Low-profile ball-grid array | Also known as laminate ball-grid array[8] | TEPBGA | Thermally-enhanced plastic ball-grid array | - | CBGA | Ceramic ball-grid array[8] | - | OBGA | Organic ball-grid array[8] | - | TFBGA | Thin fine-pitch ball-grid array[8] | - | PBGA | Plastic ball-grid array[8] | - | MAP-BGA | Mold array process - ball-grid array | - | UCSP | Micro (μ) chip-scale package | Similar to a BGA (A Maxim trademark [https://web.archive.org/web/20110714053431/http://datasheets.maxim-ic.com/en/ds/MAX9716-MAX9717.pdf example])[18] | μBGA | Micro ball-grid array | Ball spacing less than 1 mm | LFBGA | Low-profile fine-pitch ball-grid array[8] | - | TBGA | Thin ball-grid array[8] | - | SBGA | Super ball-grid array[8] | Above 500 balls | UFBGA | Ultra-fine ball-grid array[19] |
Transistor, diode, small-pin-count IC packages - MELF: Metal electrode leadless face (usually for resistors and diodes)
- SOD: Small-outline diode.
- SOT: Small-outline transistor (also SOT-23, SOT-223, SOT-323).
- TO-XX: wide range of small pin count packages often used for discrete parts like transistors or diodes.
- TO-3: Panel-mount with leads
- TO-5: Metal can package with radial leads
- TO-18: Metal can package with radial leads
- TO-39
- TO-46
- TO-66: Similar shape to the TO-3 but smaller
- TO-92: Plastic-encapsulated package with three leads
- TO-99
- TO-100
- TO-126: Plastic-encapsulated package with three leads and a hole for mounting on a heat sink
- TO-220: Through-hole plastic package with a (usually) metal heat sink tab and three leads
- TO-226[20]
- TO-247:[21] Plastic-encapsulated package with three leads and a hole for mounting on a heat sink
- TO-251:[21] Also called IPAK: SMT package similar to the DPAK but with longer leads for SMT or TH mounting
- TO-252:[21] (also called SOT428, DPAK):[21] SMT package similar to the DPAK but smaller
- TO-262:[21] Also called I2PAK: SMT package similar to the D2PAK but with longer leads for SMT or TH mounting
- TO-263:[21] Also called D2PAK: SMT package similar to the TO-220 without the extended tab and mounting hole
- TO-274:[21] Also called Super-247: SMT package similar to the TO-247 without the mounting hole
{{Anchor|PIN-PITCH}}Dimension reference Surface-mount - C
- Clearance between IC body and PCB
- H
- Total Height
- T
- Lead Thickness
- L
- Total carrier length
- LW
- Lead width
- LL
- Lead length
- P
- Pitch
{{clear left}}Through-hole- C
- Clearance between IC body and board
- H
- Total height
- T
- Lead thickness
- L
- Total carrier length
- LW
- Lead width
- LL
- Lead length
- P
- Pitch
- WB
- IC body width
- WL
- Lead-to-lead width
{{clear left}}Package dimensionsAll measurements below are given in mm. To convert mm to mils, divide mm by 0.0254 (i.e., 2.54 mm / 0.0254 = 100 mil). - C
- Clearance between package body and PCB.
- H
- Height of package from pin tip to top of package.
- T
- Thickness of pin.
- L
- Length of package body only.
- LW
- Pin width.
- LL
- Pin length from package to pin tip.
- P
- Pin pitch (distance between conductors to the PCB).
- WB
- Width of the package body only.
- WL
- Length from pin tip to pin tip on the opposite side.
{{clear left}}Dual row Image | Family | Pin | Name | Package | WB | WL | H | C | L | P | LL | T | LW |
---|
| DIP | Y}} | Dual inline package | 8-DIP | 6.2–6.48 | 7.62 | 7.7 | 9.2–9.8 | 2.54 (0.1{{nbsp}}in) | 3.05–3.6 | 1.14–1.73 | 32-DIP | 15.24 | 2.54 (0.1{{nbsp}}in) | LFCSP | N}} | Lead-frame chip-scale package | 0.5 | | MSOP | Y}} | Mini small-outline package | 8-MSOP | 3 | 4.9 | 1.1 | 0.10 | 3 | 0.65 | 0.95 | 0.18 | 0.17–0.27 | 10-MSOP | 3 | 4.9 | 1.1 | 0.10 | 3 | 0.5 | 0.95 | 0.18 | 0.17–0.27 | 16-MSOP | 3 | 4.9 | 1.1 | 0.10 | 4.04 | 0.5 | 0.95 | 0.18 | 0.17–0.27 | | SO SOIC SOP | Y}} | Small-outline integrated circuit | 8-SOIC | 3.9 | 5.8–6.2 | 1.72 | 0.10–0.25 | 4.8–5.0 | 1.27 | 1.05 | 0.19–0.25 | 0.39–0.46 | 14-SOIC | 3.9 | 5.8–6.2 | 1.72 | 0.10–0.25 | 8.55–8.75 | 1.27 | 1.05 | 0.19–0.25 | 0.39–0.46 | 16-SOIC | 3.9 | 5.8–6.2 | 1.72 | 0.10–0.25 | 9.9–10 | 1.27 | 1.05 | 0.19–0.25 | 0.39–0.46 | 16-SOIC | 7.5 | 10.00–10.65 | 2.65 | 0.10–0.30 | 10.1–10.5 | 1.27 | 1.4 | 0.23–0.32 | 0.38–0.40 | SOT | Y}} | Small-outline transistor | SOT-23-6 | 1.6 | 2.8 | 1.45 | 2.9 | 0.95 | 0.6 | 0.22–0.38 | SSOP | Y}} | Shrink small-outline package | 0.65 | TDFN | N}} | Thin dual flat no-lead | 8-TDFN | 3 | 3 | 0.7–0.8 | 3 | 0.65 | {{n/a}} | 0.19–0.3 | TSOP | Y}} | Thin small-outline package | 0.5 | TSSOP | Y}} | Thin shrink small-outline package | 8-TSSOP | 4.4 | 6.4 | 1.2 | 0.15 | 3 | 0.65 | 0.09–0.2 | 0.19–0.3 | µSOP | Y}} | Micro small-outline package[22] | µSOP-8 | 4.9 | 1.1 | 3 | 0.65 | US8[23] | Y}} | US8 package | 2.3 | 3.1 | .7 | 2 | 0.5 |
Quad rows Image | Family | Pin | Name | Package | WB | WL | H | C | L | P | LL | T | LW |
---|
PLCC | N}} | Plastic leaded chip-carrier | 1.27 | CLCC | N}} | Ceramic leadless chip-carrier | 48-CLCC | 14.22 | 14.22 | 2.21 | 14.22 | 1.016 | {{n/a}} | 0.508 | LQFP | Y}} | Low-profile Quad Flat Package | 0.50 | TQFP | Y}} | Thin quad flat-package | TQFP-44 | 10.00 | 12.00 | 0.35–0.50 | 0.80 | 1.00 | 0.09–0.20 | 0.30–0.45 | TQFN | N}} | Thin quad flat no-lead |
LGA Package | x | y | z |
---|
52-ULGA | 12{{nbsp}}mm | 17{{nbsp}}mm | 0.65{{nbsp}}mm | 52-ULGA | 14{{nbsp}}mm | 18{{nbsp}}mm | 0.10{{nbsp}}mm | 52-VELGA | ? | ? | ? |
Multi-chip packages A variety of techniques for interconnecting several chips within a single package have been proposed and researched: - SiP (system in package)
- PoP (package on package)
- 3D-SICs, Monolithic 3D ICs, and other three-dimensional integrated circuits
- WSI (wafer-scale integration)
- proximity communication[24]
See also {{portal|Electronics}}- Surface-mount technology
- Three-dimensional integrated circuit
- Interposer
- IPC (electronics)
- List of chip carriers
- List of electronics package dimensions
- Redistribution layer
- Surface-mounted package sizes
- Wafer-level packaging
References 1. ^1 2 3 4 5 6 7 8 9 10 11 12 13 14 {{cite web|url=http://www.cpushack.com/Packages.html |title=CPU Collection Museum - Chip Package Information |publisher= The CPU Shack |date= |accessdate=2011-12-15}} 2. ^{{cite web |url=http://www.national.com/ms/PA/PACKING_CONSIDERATIONS__METHODS__MATERIALS_AND_REC.pdf |title=Archived copy |accessdate=2011-02-03 |deadurl=yes |archiveurl=https://web.archive.org/web/20110815143522/http://www.national.com/ms/PA/PACKING_CONSIDERATIONS__METHODS__MATERIALS_AND_REC.pdf |archivedate=2011-08-15 |df= }} 3. ^{{cite web |url=http://www.national.com/packaging/parts/CERPACK.html |title=National Semiconductor CERPACK Package Products |publisher=National.com |date= |accessdate=2011-12-15 |deadurl=yes |archiveurl=https://web.archive.org/web/20120218205030/http://www.national.com/packaging/parts/CERPACK.html |archivedate=2012-02-18 |df= }} 4. ^{{cite web |url=http://www.national.com/packaging/parts/CQGP.html |title=National Semiconductor CQGP Package Products |publisher=National.com |date= |accessdate=2011-12-15 |deadurl=yes |archiveurl=https://web.archive.org/web/20071021023517/http://www.national.com/packaging/parts/CQGP.html |archivedate=2007-10-21 |df= }} 5. ^{{cite web |url=http://www.national.com/analog/packaging/llp |title=National's LLP Package |publisher=National.com |date= |accessdate=2011-12-15 |deadurl=yes |archiveurl=https://web.archive.org/web/20110213050709/http://www.national.com/analog/packaging/llp |archivedate=2011-02-13 |df= }} 6. ^{{cite web|url=http://www.minicaps.com/ltcc.html |title=LTCC Low Temperature Co-fired Ceramic |publisher=Minicaps.com |date= |accessdate=2011-12-15}} 7. ^{{cite book|chapter-url=http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=410760 |title=IEEE Xplore - Performance evaluation of MCM chip-to-chip interconnections using custom I/O buffer designs |pages=464–467 |doi=10.1109/ASIC.1993.410760 |publisher=Ieeexplore.ieee.org |accessdate=2011-12-15|chapter=Performance evaluation of MCM chip-to-chip interconnections using custom I/O buffer designs |year=1993 |last1=Frye |first1=R.C. |last2=Gabara |first2=T.J. |last3=Tai |first3=K.L. |last4=Fischer |first4=W.C. |last5=Knauer |first5=S.C. |isbn=978-0-7803-1375-0 }} 8. ^{{cite web |url=http://www.national.com/news/item/0,1735,1116,00.html |title=National Semiconductor Launches New Generation of Ultra-Miniature, High Pin-Count Integrated Circuit Packages |publisher=National.com |date= |accessdate=2011-12-15 |archive-url=https://web.archive.org/web/20120218205131/http://www.national.com/news/item/0,1735,1116,00.html |archive-date=2012-02-18 |dead-url=yes |df= }} 9. ^{{cite book|title=Mike Meyers' A+ Guide to PC Hardware|author1=Meyers, Michael |author2=Jernigan, Scott|url=https://books.google.com/?id=mvo5rpAX3RsC&pg=PT94&lpg=PT94&dq=PAC+%22Pin+Array+Cartridge%22#v=onepage&q=PAC%20%22Pin%20Array%20Cartridge%22&f=false|publisher=The McGraw-Hill Companies|year=2004 | isbn=978-0-07-223119-9}} 10. ^ {{webarchive |url=https://web.archive.org/web/20110818161952/http://ir.conexant.com/releasedetail.cfm?ReleaseID=431800 |date=August 18, 2011 }} 11. ^{{cite web|url=http://www.motorola.com/mediacenter/news/detail.jsp?globalObjectId=2791_2269_23 |title=Press Releases - Motorola Mobility, Inc |publisher=Motorola.com |date= |accessdate=2011-12-15}} 12. ^{{cite web|url=http://www.eetasia.com/ART_8800353559_480100_NP_9b8d1426.HTM |title=Xilinx new CPLDs with two I/O banks |publisher=Eetasia.com |date=2004-12-08 |accessdate=2011-12-15}} 13. ^{{cite web|url=http://www.chelseatech.com/packages.htm |title=Packages |publisher=Chelseatech.com |date=2010-11-15 |accessdate=2011-12-15}} 14. ^{{cite web |url=http://cpu.linuxmania.net/liste/cpuinfo/chip-package/SIDEBRAZE_DIP/chip-package-sidebraze.htm |title=Archived copy |accessdate=2009-10-24 |deadurl=yes |archiveurl=https://web.archive.org/web/20081120103405/http://cpu.linuxmania.net/liste/cpuinfo/chip-package/SIDEBRAZE_DIP/chip-package-sidebraze.htm |archivedate=2008-11-20 |df= }} 15. ^{{cite web|url=http://www.siliconfareast.com/csp.htm |title=CSP - Chip Scale Package |publisher=Siliconfareast.com |date= |accessdate=2011-12-15}} 16. ^1 {{cite web|url=http://www.chipscalereview.com/issues/ES/issues/0301/packagingFoundries.html |title=Chip Scale Review Online |publisher=Chipscalereview.com |date= |accessdate=2011-12-15}} 17. ^{{cite web |url=http://www.national.com/analog/packaging/appnote_msmd |title=Packaging Technology | National Semiconductor – Package Drawings, Part Marking, Package Codes, LLP, micro SMD, Micro-Array |publisher=National.com |date= |accessdate=2011-12-15 |deadurl=yes |archiveurl=https://web.archive.org/web/20100801065223/http://www.national.com/analog/packaging/appnote_msmd |archivedate=2010-08-01 |df= }} 18. ^1 {{cite web|url=http://www.maxim-ic.com/appnotes.cfm/an_pk/4002 |title=Understanding Flip-Chip and Chip-Scale Package Technologies and Their Applications - Maxim |publisher=Maxim-ic.com |date=2007-04-18 |accessdate=2011-12-15}} 19. ^1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 {{cite web|url=http://www.interfacebus.com/Design_Pack_Type_SOIC.html |title=Integrated Circuit, IC Package Types; SOIC. Surface Mount Device Package |publisher=Interfacebus.com |date= |accessdate=2011-12-15}} 20. ^http://www.siliconfareast.com/to226.htm 21. ^1 2 3 4 5 6 http://www.irf.com/package/ 22. ^http://pdfserv.maximintegrated.com/package_dwgs/21-0036.PDF 23. ^{{cite web |url=https://www.fairchildsemi.co.jp/collateral/product_overview/TinyLogic-Device-Product-Overview.pdf |title=Fairchild's TinyLogic family overview |date=March 22, 2013 |deadurl=yes |archiveurl=https://web.archive.org/web/20150108015729/https://www.fairchildsemi.co.jp/collateral/product_overview/TinyLogic-Device-Product-Overview.pdf |archivedate=January 8, 2015 |df= }} 24. ^{{Citation| last =| first =| year = 2004| title = Proximity Communication - the Technology| location =| page =| url = http://research.sun.com/spotlight/2004-09-20.feature-proximity.html| accessdate =| archiveurl = https://web.archive.org/web/20090718081900/http://research.sun.com/spotlight/2004-09-20.feature-proximity.html| archivedate = 2009-07-18}}
External links {{Commons category|Electronic component packages}}- JEDEC JEP95 official list of all (over 500) standard electronic packages
- [https://www.fairchildsemi.com/get-help/package-information/ Fairchild Index of Package Information]
- [https://web.archive.org/web/20131215133813/http://www.siliconfareast.com/ic-package-types.htm An illustrated listing of different package types, with links to typical dimensions/features of each]
- [https://www.jedec.org/category/technology-focus-area/jc-10/registered-outlines-jep95 JEDEC JEP95] official list of all (over 500) standard electronic packages
- Intersil packaging information
- ICpackage.org
- Solder Pad Layout Dimensions
- International Microelectronics And Packaging Society
- The Component Package Database
- Power Surface Mounts used in Power Mosfets and Radiation hardened devices
{{Semiconductor packages}}{{DEFAULTSORT:Integrated circuit packaging types}} 3 : Chip carriers|Semiconductor packages|Electronics lists |