| 释义 |
- Cyrix design (Cyrix III)
- Centaur Technology design Cyrix III, C3 C3, C7 Nano
- See also
- References
- External links
{{Expand list|date=August 2008}}This page lists x86-compliant microprocessors sold by VIA Technologies, grouped by technical merits: cores within same group have much in common. Cyrix design (Cyrix III) - All models[1] support: MMX, 3DNow!
Marketing
name | Core | Frequency | Front-side bus | L1-cache | L2-cache | FPU
speed | Pipeline
stages | Typical power | Voltage | Process | | Cyrix III | Joshua | 350-450 MHz | 100-133 MHz | 64 KB | 256 KB | 100% | ? | 13-16 W | 2.2 V | 180 nm Al |
Centaur Technology design Cyrix III, C3 - All models[2] support: MMX, 3DNow!
Marketing
name | Core | Frequency | Front-side bus | L1 cache | L2 cache | FPU
speed | Pipeline
stages | Typical power | Voltage | Process | | Cyrix III, C3, 1GigaPro | Samuel (C5A) | 466-733 MHz | 100-133 MHz | 128 KB | 0 KB | 50% | 12 | 6.8-10.6 W | 1.8-2.0 V | 180 nm Al | | Cyrix III, C3, 1GigaPro, Eden ESP, XP 2000+ | Samuel 2 (C5B) | 600-800 MHz | 100-133 MHz | 128 KB | 64 KB | 50% | 12 | 5.8-6.6 W | 1.5-1.65 V | 150 nm Al | | C3, Eden ESP | Ezra (C5C) | 733-933 MHz | 100-133 MHz | 128 KB | 64 KB | 50% | 12 | 5.3-5.9 W | 1.35 V | 130 nm Al | | C3 | Ezra-T (C5N) | 800-1000 MHz | 100-133 MHz | 64 KB | 64 KB | 50% | 12 | 5.3-11.8 W | 1.35 V | 130 nm Al |
C3, C7 - All models[3] support: MMX, SSE
- SSE2, SSE3, NX bit supported by Esther (C5J)
Marketing
name | Core | Frequency | Front-side bus | L1 cache | L2 cache | FPU
speed | Pipeline
stages | Typical power | Voltage | Process | | C3, Eden ESP, Eden-N | Nehemiah (C5XL) | 800-1400 MHz | 133 MHz | 64 KB | 64 KB | 100% | 16 | 15-19 W | 1.25-1.45 V | 130 nm Cu | | C3 | Nehemiah+ (C5P) | 1-1.4 GHz | 133 MHz | 32 KB | 64 KB | 100% | 16 | 11-12 W | 1.25 V | 130 nm Cu | | C7, C7-D, C7-M, Eden, Eden ULV | Esther (C5J) | 0.4-2.0 GHz | 400-533 MT/s | 32 KB | 128 KB | 100% | 16 | 12-20 W | 0.9-1.1(?) V | 90 nm SOI |
| Series | Model | Core | Frequency
[MHz] | Front-side bus
[MHz] | Year | Process
[nm] | Package size
[mm2] | Power
[W] | L2 cache
[K] | L1 I/D cache
[K] | Performance
[SPEC2000] |
|---|
| Eden | Eden ESP | Samuel 2 | 300–600 | 66/100/133 | 2001 | 150 | 35×35 | 2.5–6 | 64 | 64/64 | {{unk}} |
|---|
| Eden ESP | Nehemiah | 667–1000 | 133/200 | 2003–2004 | 130 | 35×35 | 6–7 | 64 | 64/64 | {{unk}} | | Eden-N | Nehemiah | 533–1000 | 133 | 2003 | 130 | 15×15 | 2.5–7 | 64 | 64/64 | {{unk}} | | Eden | Esther | 400–1500 | 400–800 | 2006–2007 | 90 | 30 | <7.5 | 128 | 32/32 | {{unk}} | | Eden X2 | {{unk}} | 800 | {{unk}} | 2011 | 40 | 11×6 | {{unk}} | {{unk}} | {{unk}} | {{unk}} | | C3 | C3 | Samuel 2 | 667–800 | 100–133 | 2001 | 150 | {{unk}} | 13 | 64 | 64/64 | {{unk}} |
|---|
| C3 | Ezra | 800–1000 | 100–133 | 2002 | 130 | {{unk}} | 8.3–10 | 64 | 64/64 | {{unk}} | | C3 | Nehemiah | 1000–1400 | 133–200 | 2003 | 130 | 35×35 | 15–21 | 64 | 64/64 | {{unk}} | | C3-M | Nehemiah | 1000–1400 | 133–200 | 2003 | 130 | 35×35 | 11–19 | 64 | 64/64 | {{unk}} | | C7 | C7-D | Esther | 1500–1800 | 400 | 2006 | 90 | 21×21 | 20–25 | 128 | 16/16 | {{unk}} |
|---|
| C7-M | Esther | 1000–2000 | 400 | 2005 | 90 | 21×21 | 12–20 | 128 | 16/16 | {{unk}} | | C7 | Esther | 1500–2000 | 800 | 2007 | 90 | 21×21 | 12–20 | 128 | 16/16 | {{unk}} | 17.1/14.5 rate[4]> | QuadCore | QuadCore | Isaiah | 1000-1460 | 1066 | 2011 | 40 | 21×21 | 27.5 | 4× 1024[5] | 4× 64/64 | 30.1/24.1 rate[6] |
|---|
Nano - See List of Nano microprocessors
See also - List of VIA C3 microprocessors
- List of VIA C7 microprocessors
- List of VIA Eden microprocessors
- List of VIA Nano microprocessors
References 1. ^{{cite web | title = IA-32 implementation: VIA Cyrix III | publisher = sandpile.org | url = http://sandpile.org/impl/m2c3.htm | accessdate = 2007-07-23 | deadurl = yes | archiveurl = https://web.archive.org/web/20070709200826/http://www.sandpile.org/impl/m2c3.htm | archivedate = 2007-07-09 | df = }}
2. ^{{cite web | title = IA-32 implementation: VIA C3 | publisher = sandpile.org | url = http://sandpile.org/impl/c5.htm | accessdate = 2007-07-23 | deadurl = yes | archiveurl = https://web.archive.org/web/20070717014946/http://www.sandpile.org/impl/c5.htm | archivedate = 2007-07-17 | df = }}
3. ^{{cite web | title = IA-32 implementation: VIA C7 | publisher = sandpile.org | url = http://sandpile.org/impl/c5xl.htm | accessdate = 2007-07-23 | deadurl = yes | archiveurl = https://web.archive.org/web/20070630151130/http://www.sandpile.org/impl/c5xl.htm | archivedate = 2007-06-30 | df = }}
4. ^{{cite web |url=http://www.via.com.tw/en/products/processors/nanoX2/whitepaper.jsp |title=VIA Nano X2 SPEC2000 ratio and rate scores |publisher=Via.com |accessdate=2014-02-03 |deadurl=yes |archiveurl=https://web.archive.org/web/20140207105837/http://www.via.com.tw/en/products/processors/nanoX2/whitepaper.jsp |archivedate=7 February 2014 |df=dmy-all }}
5. ^{{cite web |url=http://www.via.com.tw/en/products/processors/quadcore/index.jsp |title=VIA QuadCore Processor |publisher=Via.com |accessdate=2014-02-03}}
6. ^{{cite web |url=http://www.via.com.tw/en/downloads/whitepapers/processors/NanoX2_whitepaper_201107.pdf |title=VIA Nano X2 Whitepaper |publisher=Via.com |accessdate=2014-02-03 |deadurl=yes |archiveurl=https://web.archive.org/web/20120527051549/http://www.via.com.tw/en/downloads/whitepapers/processors/NanoX2_whitepaper_201107.pdf |archivedate=27 May 2012 |df=dmy-all }}
External links - Via C3 product page
- Via C7 product page
- Via Nano product page
{{VIA}} 1 : Lists of microprocessors |