“Stack register”的意思、由来-开放百科全书

A stack register is a computer central processor register whose purpose is to keep track of a call stack. On an accumulator-based architecture machine, this may be a dedicated register such as SP on an Intel x86 machine. On a general register machine, it may be a register which is reserved by convention, such as on the PDP-11 or RISC machines. Some designs such as the Data General Eclipse had no dedicated register, but used a reserved hardware memory address for this function.

Machines before the late 1960s—such as the PDP-8 and HP 2100—did not have compilers which supported recursion. Their subroutine instructions typically would save the current location in the jump address, and then set the program counter to the next address.^[1] While this is simpler than maintaining a stack, since there is only one return location per subroutine code section, there cannot be recursion without considerable effort on the part of the programmer.

A stack machine has 2 or more stack registers — one of them keeps track of a call stack, the other(s) keep track of other stack(s).

Stack registers in x86

In 8086, the main stack register is called stack pointer - SP. The stack segment

register (SS) is usually used to store information about the memory segment that stores the call stack of currently executed program. SP points to current stack top. By default, the stack grows downward in memory, so newer values are placed at lower memory addresses.

To push a value to the stack, the PUSH instruction is used. To pop a value from the stack,

Example: Assuming that SS = 1000h and SP = 0xF820. This means that current stack top is the physical address 0x1F820 (this is due to memory segmentation in 8086). The next two machine instructions of the program are:

This illustrates how PUSH works. Usually, the running program pushes registers to the stack to

make use of the registers for other purposes, like to call a routine that may change the current

values of registers. To restore the values stored at the stack, the program shall contain

NOTE: In 8086, PUSH & POP instructions can only work with 16-bit elements.

Stack engine

Simpler processors store the stack pointer in a regular hardware register and use the arithmetic logic unit (ALU) to manipulate its value. Typically push and pop are translated into multiple micro-ops, to separately add/subtract the stack pointer, and perform the load/store in memory.^[3]

Newer processors contain a dedicated stack engine to optimize stack operations. Pentium M was the first x86 processor to introduce a stack engine. In its implementation, the stack pointer is split among two registers: ESP_O, which is a 32-bit register, and ESP_d, an 8-bit delta value that is updated directly by stack operations. PUSH, POP, CALL and RET opcodes operate directly with the ESP_d register. If ESP_d is near overflow or the ESP register is referenced from other instructions (when ESP_d ≠ 0), a synchronisation micro-op is inserted that updates the ESP_O using the ALU and resets ESP_d to 0. This design has remained largely unmodified in later Intel processors, although ESP_O has been expanded to 64 bits.^[4]

A stack engine similar to Intel's was also adopted in the AMD K8 microarchitecture. In Bulldozer, the need for synchronization micro-ops was removed, but the internal design of the stack engine is not known.^[4]

References

1. ^{{cite book| author = David Salomon| title = Assemblers and Loaders|date=February 1993| publisher = Ellis Horwood Ltd. | isbn = 0-13-052564-2| url = http://www.davidsalomon.name/assem.advertis/asl.pdf| accessdate = 2008-10-01| quote = Most computers save the return address in either the stack, in one of the registers, or in the first word of the procedure (in which case the first executable instruction of the procedure should be stored in the second word). If the latter method is used, a return from the procedure is a jump to the memory location whose address is contained in the first word of the procedure.}}
2. ^{{cite web|last=Howard|first=Brian|title=Assembly Tutorial - Instructions|url=http://www.csc.depauw.edu/~bhoward/asmtut/asmtut4.html|work=Computer Science Department, DePauw University|accessdate=19 July 2013}}
3. ^{{Cite web|url=http://archive.arstechnica.com/cpu/004/pentium-m/m-pentium-m-5.html|title=A Look at Centrino's Core: The Pentium M|author=Jon "Hannibal" Stokes|date=25 February 2004|website=archive.arstechnica.com|publisher=|page=5}}
4. ^¹{{Cite web|url=http://www.agner.org/optimize/microarchitecture.pdf|title=The microarchitecture of Intel, AMD and VIA CPUs|last=Fog|first=Agner|date=|website=|publisher=Technical University of Denmark|access-date=}}