“Timing closure”的意思、由来-开放百科全书

Timing closure is the process by which a logic design consisting of primitive elements such as combinatorial logic gates (and, or, not, nand, nor, etc.) and sequential logic gates (flip flops, latches, memories) is modified to meet its timing requirements. Unlike in a computer program where there is no explicit delay to perform a calculation, logic circuits have intrinsic and well defined delays to propagate inputs to outputs. In simple cases, the user can compute the path delay between elements manually. If the design is more than a dozen or so elements this is impractical. For example, the time delay along a path from the output of a D-Flip Flop, through combinatorial logic gates, then into the next D-Flip Flop input must satisfy (be less than) the time period between synchronizing clock pulses to the two flip flops. When the delay through the elements is greater than the clock cycle time, the elements are said to be on the critical path. The circuit will not function when the path delay exceeds the clock cycle delay so modifying the circuit to remove the timing failure (and eliminate the critical path) is an important part of the logic design engineer's task.

Many times logic circuit changes are handled by user's EDA tools based on timing constraint directives prepared by a designer. The term is also used for the goal that is achieved, when such a design has reached the end of the flow and its timing requirements are satisfied.

The main steps of the design flow, which may be involved in this process, are logic synthesis, placement, clock-tree synthesis and routing. With present technologies all of them need to be timing-aware for a design to properly meet its timing requirements, but with technologies in the range of the micrometre only logic synthesis EDA tools had such a prerequisite.

Nevertheless, even if timing-awareness was extended to all these steps starting from well-established principles used for logic synthesis, the two phases, logic and physical, of the timing closure process are conventionally handled by different design teams and different EDA tools. [https://web.archive.org/web/20070228233817/http://www.synopsys.com/products/logic/design_compiler.html Design Compiler] by Synopsys, Encounter RTL Compiler by Cadence Design Systems and BlastCreate by Magma Design Automation are examples of logic synthesis tools. [https://web.archive.org/web/20070206065723/http://www.synopsys.com/products/iccompiler/iccompiler.html IC Compiler] by Synopsys, SoC Encounter by Cadence Design Systems and Blast Fusion by Magma Design Automation are examples of tools capable of timing-aware placement, clock tree synthesis and routing and therefore used for physical timing closure.

When the user requires the circuit to meet exceptionally difficult timing constraints, it may be necessary to utilize machine learning^[1] [https://www.plunify.com/en/intime/ programs] to find an optimum set of FPGA synthesis, map, place and route tool configuration parameters that ensures the circuit will close timing.

A timing requirement needs to be translated into a static timing constraint for an EDA tool to be able to handle it.

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