- Background
- Technology production history
- 10 nm process nodes Foundry DRAM
- References
|reason=Still an issue regarding 10nm/7nm terminology that isn't addressed in the 10 nanometer and 7 nanometer is a deviation from the International Technology Roadmap for Semiconductors definitions. In short, 7 nm Samsung/TSMC is equivalent to 10 nm Intel. Thus treating 10 nm Intel and 7 nm Samsung/TSMC at different articles due to marketing material not real measurements seems to be incorrect, specially when the pages refer to ITRS roadmap (duplicate note at other affected article}}{{Semiconductor manufacturing processes}}
In semiconductor fabrication, the International Technology Roadmap for Semiconductors (ITRS) defines the 10 nanometer (10 nm) node as the technology node following the 14 nm node. "10 nm class" denotes chips made using process technologies between 10 and 20 nanometers. The 10 nm process from Intel is the same as the 7 nm processes offered by Samsung and TSMC, thus, what really matters beyond 10 nm is transistor density(number of transistors per square milimeter), not transistor size.
All production "10 nm" processes are based on silicon CMOS finFET technology. Samsung first started their production of "10 nm" chips in 2016; with product shipments following through in 2017 in the form of Galaxy S8.
Background
The ITRS's original naming of this technology node was "11 nm". According to the 2007 edition of the roadmap, by the year 2022, the half-pitch (i.e., half the distance between identical features in an array) for a DRAM should be 11 nm.
In 2008, Pat Gelsinger, at the time serving as Intel's Chief Technology Officer, said that Intel saw a 'clear way' towards the 10 nm node.[1][2]
In actuality, "10 nm" as it is generally understood in 2018 is only in high-volume production at Samsung. GlobalFoundries has skipped 10 nm, Intel has not yet started high-volume 10 nm production, due to yield issues, and TSMC has considered 10 nm to be a short-lived node,[3] mainly dedicated to processors for Apple during 2017–2018, moving on to 7 nm in 2018.
There is also a distinction to be made between 10 nm as marketed by foundries and 10 nm as marketed by DRAM companies.
Technology production history
On 17 October 2016, Samsung Electronics announced mass production at 10 nm.[4] The technology's main announced challenge has been triple patterning for its metal layer.[5][6]
On 21 April 2017, Samsung started shipping their Galaxy S8 smartphone which uses the company's version of the 10 nm processor.[7]
On 12 June 2017, Apple delivered second-generation iPad Pro tablets powered with TSMC-produced Apple A10X chips using the 10 nm FinFET process.[8]
On September 12, 2017, Apple announced the Apple A11, a 64-bit ARM-based system on a chip, manufactured by TSMC using a 10 nm FinFET process and containing 4.3 billion transistors on a die of 87.66 mm2.
In April 2018, Intel announced a delay in volume production of 10 nm mainstream CPUs until sometime in 2019.[9] In July the exact time was further pinned down to the holiday season.[10] In the meantime, however, they did release a low-power 10 nm mobile chip, albeit exclusive to Chinese markets.[11]
10 nm process nodes
Foundry
| ITRS Logic Device Ground Rules | Intel (limited) | TSMC | Samsung | ITRS Logic Device Ground Rules | |
|---|---|---|---|---|---|
| Process name | 11/10 nm | (2018){{efn>Measurements of the process used for Cannon Lake in 2018. It is unclear whether these will be the same for Intel's next 10nm process in 2019.[12]}} | 10 nm | 10 nm | 16/14 nm |
| Transistor density (MTr / mm²) | {{N/A}} | [13]{{efn>Intel uses this formula:[14]  }} | {{Unknown}} | {{Unknown}} | {{N/A}} |
| Transistor Gate Pitch (nm) | 48 | 54 | 66 | 68 | 70 |
| Interconnect pitch (nm) | 36 | 36 | 44 | 51 | 56 |
| Transistor Fin Pitch (nm) | 36 | 34 | 36 | 42 | 42 |
| Transistor Fin Height (nm) | 42 | 53 | {{Unknown}} | 49 | 42 |
Transistor gate pitch is also referred to as CPP (contacted poly pitch) and interconnect pitch is also referred to as MMP (minimum metal pitch). Samsung reported their 10 nm process as having a 64 nm transistor gate pitch and 48 nm interconnect pitch. TSMC reported their 10 nm process as having a 64 nm transistor gate pitch and 42 nm interconnect pitch. Further investigation by Tech Insights revealed these values to be false and they have been updated accordingly. In addition, the transistor fin height of Samsung's 10 nm process was updated by MSSCORPS CO at SEMICON Taiwan 2017.[15][16][17][18][19]
DRAM
For the DRAM industry, the "10 nm" node is often referred to as "10 nm-class" and this dimension generally refers to the half-pitch of the active area. The "10 nm" foundry structures are generally much larger. Samsung is also the most prominent player for 10 nm-class DRAM.[20]
References
2. ^{{cite web|title=MIT: Optical lithography good to 12 nanometers |url=http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=209400807 |work= |archiveurl=https://www.webcitation.org/5hjItyFjG?url=http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=209400807 |archivedate=2009-06-22 |deadurl=no |accessdate=2009-06-20 |df= }}
3. ^10nm rollout
4. ^{{citation| url = https://news.samsung.com/global/samsung-starts-industrys-first-mass-production-of-system-on-chip-with-10-nanometer-finfet-technology | title = Samsung Starts Industry’s First Mass Production of System-on-Chip with 10-Nanometer FinFET Technology| date = Oct 2016 }}
5. ^[https://news.samsung.com/global/samsung-starts-industrys-first-mass-production-of-system-on-chip-with-10-nanometer-finfet-technology Samsung 10nm announcement]
6. ^triple patterning for 10nm metal
7. ^http://www.samsung.com/us/explore/galaxy-s8/buy/
8. ^{{Cite web|url=http://www.techinsights.com/about-techinsights/overview/blog/10nm-rollout-marching-right-along/|title=10nm Rollout Marching Right Along|last=techinsights.com|website=www.techinsights.com|access-date=2017-06-30}}
9. ^{{cite web|url=https://www.fool.com/investing/2018/04/29/intel-corp-delays-10nm-chip-production.aspx|title=Intel Corp. Delays 10nm Chip Production - Mass production is now scheduled for 2019.|date=2018-04-29|access-date=2018-08-01}}
10. ^{{cite news|url=https://arstechnica.com/gadgets/2018/07/intel-says-not-to-expect-mainstream-10nm-chips-until-2h19/|title=Intel says not to expect mainstream 10nm chips until 2H19|date=2018-07-28|access-date=2018-08-01}}
11. ^{{cite web|url=https://www.tomshardware.com/news/intel-10nm-processor-core-i3-8121u,37054.html|title=Intel's First 10nm Processor Lands In China|date=2018-05-15|access-date=2018-09-11}}
12. ^{{cite web|url=https://semiaccurate.com/2018/08/02/intel-guts-10nm-to-get-it-out-the-door/|title=Intel guts 10nm to get it out the door|last=Demerjian|first=Charlie|date=2018-08-02|work=SemiAccurate|accessdate=29 September 2018}}
13. ^{{Cite news|url=https://hexus.net/tech/news/cpu/119699-intel-10nm-density-27x-improved-14nm-node/|title=Intel 10nm density is 2.7X improved over its 14nm node|work=HEXUS|access-date=2018-11-14|language=en-GB}}
14. ^{{Cite web|url=https://newsroom.intel.com/editorials/lets-clear-up-node-naming-mess/|title=Let’s Clear Up the Node Naming Mess|last=Bohr|first=Mark|date=2017-03-28|website=Intel Newsroom|access-date=2018-12-06}}
15. ^{{Cite web|url=http://hothardware.com/news/intel-details-advanced-10nm-node|title=Intel Details Cannonlake's Advanced 10nm FinFET Node, Claims Full Generation Lead Over Rivals}}
16. ^{{Cite web|url=https://www.semiconductors.org/wp-content/uploads/2018/06/0_2015-ITRS-2.0-Executive-Report-1.pdf|title=International Technology Roadmap for Semiconductors 2.0 2015 Edition Executive Report|access-date=2018-12-27}}
17. ^{{Cite web|url=https://www.semiwiki.com/forum/content/6713-14nm-16nm-10nm-7nm-what-we-know-now.html|title=14nm 16nm 10nm and 7nm - What we know now}}
18. ^{{Cite web|url=http://www.techinsights.com/about-techinsights/overview/blog/qualcomm-snapdragon-835-first-to-10-nm/|title=Qualcomm Snapdragon 835 First to 10 nm |quote="Samsung 10LPE process" }}
19. ^{{Cite web|url=https://en.wikichip.org/wiki/10_nm_lithography_process|title=10 nm lithography process |website=wikichip}}
20. ^[https://news.samsung.com/global/samsung-begins-mass-production-of-10nm-class-16gb-lpddr4x-dram-for-automobiles Samsung 10nm-class LPDDR4X]
| prev=14 nm
| next=7 nm
| list=CMOS manufacturing processes
}}{{DEFAULTSORT:10 nanometer}}
- Dolf van der nagel
- Dolf van der Nagel
- Dolgarrog
- Dolgarrog railway station
- Dolgaunt
- Dolgellau railway station
- Dolgen am see
- Dolgen am See
- Dolgesheim
- Dolgeville
- Dolgoch railway station
- Dolgolsren Sumiyabazar
- Dolgoprudniy
- Dolgoprudny
- Dolgorouki
- Dolgoroukov
- Dolgorsuren Dagvadorj
- Dolgorsuren Serjbudee
- Dolgorsuren Sumiyabazar
- Dolgorsürengiin Serjbüdee
- Dolgorsürengiin Sumyaabazar
- Dolgoruki
- Dolgoruky Family
- Dol Guldor
- Dol Guldur (album)