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词条 Advanced Vector Extensions
释义

  1. {{Anchor|AVX1}}Advanced Vector Extensions

      New instructions    CPUs with AVX    Compiler and assembler support    Operating system support  

  2. {{Anchor|AVX2}}Advanced Vector Extensions 2

      New instructions    CPUs with AVX2  

  3. AVX-512

      CPUs with AVX-512    Compilers supporting AVX-512  

  4. Applications

      Software  

  5. See also

  6. References

  7. External links

{{short description|Extensions to the x86 instruction set architecture for microprocessors from Intel and AMD}}{{Use mdy dates|date=September 2018}}

Advanced Vector Extensions (AVX, also known as Sandy Bridge New Extensions) are extensions to the x86 instruction set architecture for microprocessors from Intel and AMD proposed by Intel in March 2008 and first supported by Intel with the Sandy Bridge[1] processor shipping in Q1 2011 and later on by AMD with the Bulldozer[2] processor shipping in Q3 2011. AVX provides new features, new instructions and a new coding scheme.

AVX2 expands most integer commands to 256 bits and introduces fused multiply-accumulate (FMA) operations. AVX-512 expands AVX to 512-bit support using a new EVEX prefix encoding proposed by Intel in July 2013 and first supported by Intel with the Knights Landing processor, which shipped in 2016.[3][4]

{{Anchor|AVX1}}Advanced Vector Extensions

AVX uses sixteen YMM registers. Each YMM register contains:

  • eight 32-bit single-precision floating point numbers or
  • four 64-bit double-precision floating point numbers.

The width of the SIMD register file is increased from 128 bits to 256 bits, and renamed from XMM0–XMM7 to YMM0–YMM7 (in x86-64 mode, YMM0–YMM15). In processors with AVX support, the legacy SSE instructions (which previously operated on 128-bit XMM registers) can be extended using the VEX prefix to operate on the lower 128 bits of the YMM registers.

AVX-512 register scheme as extension from the AVX (YMM0-YMM15) and SSE (XMM0-XMM15) registers
511 256255 128127 0
  ZMM0    YMM0    XMM0  
ZMM1YMM1XMM1
ZMM2YMM2XMM2
ZMM3YMM3XMM3
ZMM4YMM4XMM4
ZMM5YMM5XMM5
ZMM6YMM6XMM6
ZMM7YMM7XMM7
ZMM8YMM8XMM8
ZMM9YMM9XMM9
ZMM10YMM10XMM10
ZMM11YMM11XMM11
ZMM12YMM12XMM12
ZMM13YMM13XMM13
ZMM14YMM14XMM14
ZMM15YMM15XMM15
ZMM16YMM16XMM16
ZMM17YMM17XMM17
ZMM18YMM18XMM18
ZMM19YMM19XMM19
ZMM20YMM20XMM20
ZMM21YMM21XMM21
ZMM22YMM22XMM22
ZMM23YMM23XMM23
ZMM24YMM24XMM24
ZMM25YMM25XMM25
ZMM26YMM26XMM26
ZMM27YMM27XMM27
ZMM28YMM28XMM28
ZMM29YMM29XMM29
ZMM30YMM30XMM30
ZMM31YMM31XMM31

AVX introduces a three-operand SIMD instruction format, where the destination register is distinct from the two source operands. For example, an SSE instruction using the conventional two-operand form a = a + b can now use a non-destructive three-operand form c = a + b, preserving both source operands. AVX's three-operand format is limited to the instructions with SIMD operands (YMM), and does not include instructions with general purpose registers (e.g. EAX). Such support will first appear in AVX2.[5]

The alignment requirement of SIMD memory operands is relaxed.[5]

The new VEX coding scheme introduces a new set of code prefixes that extends the opcode space, allows instructions to have more than two operands, and allows SIMD vector registers to be longer than 128 bits. The VEX prefix can also be used on the legacy SSE instructions giving them a three-operand form, and making them interact more efficiently with AVX instructions without the need for VZEROUPPER and VZEROALL.

The AVX instructions support both 128-bit and 256-bit SIMD. The 128-bit versions can be useful to improve old code without needing to widen the vectorization, and avoid the penalty of going from SSE to AVX, they are also faster on some early AMD implementations of AVX. This mode is sometimes known as AVX-128.[6]

New instructions

These AVX instructions are in addition to the ones that are 256-bit extensions of the legacy 128-bit SSE instructions; most are usable on both 128-bit and 256-bit operands.

Instruction Description
VBROADCASTSS, VBROADCASTSD, VBROADCASTF128 Copy a 32-bit, 64-bit or 128-bit memory operand to all elements of a XMM or YMM vector register.
VINSERTF128 Replaces either the lower half or the upper half of a 256-bit YMM register with the value of a 128-bit source operand. The other half of the destination is unchanged.
VEXTRACTF128 Extracts either the lower half or the upper half of a 256-bit YMM register and copies the value to a 128-bit destination operand.
VMASKMOVPS, VMASKMOVPD Conditionally reads any number of elements from a SIMD vector memory operand into a destination register, leaving the remaining vector elements unread and setting the corresponding elements in the destination register to zero. Alternatively, conditionally writes any number of elements from a SIMD vector register operand to a vector memory operand, leaving the remaining elements of the memory operand unchanged. On the AMD Jaguar processor architecture, this instruction with a memory source operand takes more than 300 clock cycles when the mask is zero, in which case the instruction should do nothing. This appears to be a design flaw.[7]
VPERMILPS, VPERMILPD Permute In-Lane. Shuffle the 32-bit or 64-bit vector elements of one input operand. These are in-lane 256-bit instructions, meaning that they operate on all 256 bits with two separate 128-bit shuffles, so they can not shuffle across the 128-bit lanes.[8]
VPERM2F128 Shuffle the four 128-bit vector elements of two 256-bit source operands into a 256-bit destination operand, with an immediate constant as selector.
VZEROALL Set all YMM registers to zero and tag them as unused. Used when switching between 128-bit use and 256-bit use.
VZEROUPPER Set the upper half of all YMM registers to zero. Used when switching between 128-bit use and 256-bit use.

CPUs with AVX

  • Intel
    • Sandy Bridge processor, Q1 2011[9]
    • Sandy Bridge E processor, Q4 2011[10]
    • Ivy Bridge processor, Q1 2012
    • Ivy Bridge E processor, Q3 2013
    • Haswell processor, Q2 2013
    • Haswell E processor, Q3 2014
    • Broadwell processor, Q4 2014
    • Broadwell E processor, Q2 2016
    • Skylake processor, Q3 2015
    • Kaby Lake processor, Q3 2016(ULV mobile)/Q1 2017(desktop/mobile)
    • Skylake-X processor, Q2 2017
    • Coffee Lake processor, Q4 2017
    • Cannon Lake (microarchitecture) processor, Q2 2018
    • Cascade Lake processor, Q4 2018
    • Ice Lake processor, expected in 2019

Note: Not all CPUs from the listed families support AVX. Generally, CPUs with the commercial denomination "Core i3/i5/i7" support them, whereas "Pentium" and "Celeron" CPUs don't.

  • AMD:
    • Jaguar-based processors and newer
    • Puma-based processors and newer
    • "Heavy Equipment" processors
    • Bulldozer-based processors, Q4 2011[11]
    • Piledriver-based processors, Q4 2012[12]
    • Steamroller-based processors, Q1 2014
    • Excavator-based processors and newer, 2015
    • Zen-based processors, Q1 2017
    • Zen+-based processors, Q2 2018

Issues regarding compatibility between future Intel and AMD processors are discussed under XOP instruction set.

Compiler and assembler support

GCC starting with version 4.6 (although there was a 4.3 branch with certain support) and the Intel Compiler Suite starting with version 11.1 support AVX. The Visual Studio 2010/2012 compiler supports AVX via intrinsic and /arch:AVX switch. The Open64 compiler version 4.5.1 supports AVX with -mavx flag. Absoft supports with -mavx flag. PathScale supports via the -mavx flag. The Free Pascal compiler supports AVX and AVX2 with the -CfAVX and -CfAVX2 switches from version 2.7.1. The Vector Pascal compiler supports AVX via the -cpuAVX32 flag. The GNU Assembler (GAS) inline assembly functions support these instructions (accessible via GCC), as do Intel primitives and the Intel inline assembler (closely compatible to GAS, although more general in its handling of local references within inline code). Other assemblers such as MASM VS2010 version, YASM,[13] FASM, NASM and JWASM.

Operating system support

AVX adds new register-state through the 256-bit wide YMM register file, so explicit operating system support is required to properly save and restore AVX's expanded registers between context switches. The following operating system versions support AVX:

  • DragonFly BSD: support added in early 2013.
  • FreeBSD: support added in a patch submitted on January 21, 2012,[14] which was included in the 9.1 stable release[15]
  • Linux: supported since kernel version 2.6.30,[16] released on June 9, 2009.[17]
  • macOS: support added in 10.6.8 (Snow Leopard) update[18] released on June 23, 2011.
  • OpenBSD: support added on March 21, 2015.[19]
  • Solaris: supported in Solaris 10 Update 10 and Solaris 11
  • Windows: supported in Windows 7 SP1 and Windows Server 2008 R2 SP1,[20] Windows 8, Windows 10
    • Windows Server 2008 R2 SP1 with Hyper-V requires a hotfix to support AMD AVX (Opteron 6200 and 4200 series) processors, KB2568088

{{Anchor|AVX2}}Advanced Vector Extensions 2

Advanced Vector Extensions 2 (AVX2), also known as Haswell New Instructions,[21] is an expansion of the AVX instruction set introduced in Intel's Haswell microarchitecture. AVX2 makes the following additions:

  • expansion of most vector integer SSE and AVX instructions to 256 bits
  • three-operand general-purpose bit manipulation and multiply
  • Gather support, enabling vector elements to be loaded from non-contiguous memory locations
  • DWORD- and QWORD-granularity any-to-any permutes
  • vector shifts.

Sometimes another extension using a different cpuid flag is considered part of AVX2; those instructions are listed on their own page and not below:

  • three-operand fused multiply-accumulate support (FMA3)

New instructions

Instruction Description
VBROADCASTSS, VBROADCASTSD Copy a 32-bit or 64-bit register operand to all elements of a XMM or YMM vector register. These are register versions of the same instructions in AVX1. There is no 128-bit version however, but the same effect can be simply achieved using VINSERTF128.
VPBROADCASTB, VPBROADCASTW, VPBROADCASTD, VPBROADCASTQ Copy an 8, 16, 32 or 64-bit integer register or memory operand to all elements of a XMM or YMM vector register.
VBROADCASTI128 Copy a 128-bit memory operand to all elements of a YMM vector register.
VINSERTI128 Replaces either the lower half or the upper half of a 256-bit YMM register with the value of a 128-bit source operand. The other half of the destination is unchanged.
VEXTRACTI128 Extracts either the lower half or the upper half of a 256-bit YMM register and copies the value to a 128-bit destination operand.
VGATHERDPD, VGATHERQPD, VGATHERDPS, VGATHERQPS Gathers single or double precision floating point values using either 32 or 64-bit indices and scale.
VPGATHERDD, VPGATHERDQ, VPGATHERQD, VPGATHERQQ Gathers 32 or 64-bit integer values using either 32 or 64-bit indices and scale.
VPMASKMOVD, VPMASKMOVQ Conditionally reads any number of elements from a SIMD vector memory operand into a destination register, leaving the remaining vector elements unread and setting the corresponding elements in the destination register to zero. Alternatively, conditionally writes any number of elements from a SIMD vector register operand to a vector memory operand, leaving the remaining elements of the memory operand unchanged.
VPERMPS, VPERMD Shuffle the eight 32-bit vector elements of one 256-bit source operand into a 256-bit destination operand, with a register or memory operand as selector.
VPERMPD, VPERMQ Shuffle the four 64-bit vector elements of one 256-bit source operand into a 256-bit destination operand, with a register or memory operand as selector.
VPERM2I128 Shuffle the four 128-bit vector elements of two 256-bit source operands into a 256-bit destination operand, with an immediate constant as selector.
VPBLENDD Doubleword immediate version of the PBLEND instructions from SSE4.
VPSLLVD, VPSLLVQ Shift left logical. Allows variable shifts where each element is shifted according to the packed input.
VPSRLVD, VPSRLVQ Shift right logical. Allows variable shifts where each element is shifted according to the packed input.
VPSRAVD Shift right arithmetically. Allows variable shifts where each element is shifted according to the packed input.

CPUs with AVX2

  • Intel
    • Haswell processor (only Core branded), Q2 2013
    • Haswell E processor (only Core branded), Q3 2014
    • Broadwell processor (only Core branded), Q4 2014
    • Broadwell E processor (only Core branded), Q3 2016
    • Skylake processor (only Core branded), Q3 2015
    • Kaby Lake processor (only Core branded), Q3 2016(ULV mobile)/Q1 2017(desktop/mobile)
    • Skylake-X processor (only Core branded), Q2 2017
    • Coffee Lake processor (only Core branded), Q4 2017
    • Cannon Lake processor, Q2 2018
    • Cascade Lake processor, Q4 2019
    • Ice Lake processor, expected in 2019
  • AMD
    • Excavator processor and newer, Q2 2015
    • Zen processor, Q1 2017
    • Zen+ processor, Q2 2018

AVX-512

{{Main article|AVX-512}}AVX-512 are 512-bit extensions to the 256-bit Advanced Vector Extensions SIMD instructions for x86 instruction set architecture proposed by Intel in July 2013, and scheduled to be supported in 2015 with Intel's Knights Landing processor.[3]

AVX-512 instruction are encoded with the new EVEX prefix. It allows 4 operands, 7 new 64-bit opmask registers, scalar memory mode with automatic broadcast, explicit rounding control, and compressed displacement memory addressing mode. The width of the register file is increased to 512 bits and total register count increased to 32 (registers ZMM0-ZMM31) in x86-64 mode.

AVX-512 consists of multiple extensions not all meant to be supported by all processors implementing them. The instruction set consists of the following:

  • AVX-512 Foundation{{snd}} adds several new instructions and expands most 32-bit and 64-bit floating point SSE-SSE4.1 and AVX/AVX2 instructions with EVEX coding scheme to support the 512-bit registers, operation masks, parameter broadcasting, and embedded rounding and exception control
  • AVX-512 Conflict Detection Instructions (CD){{snd}} efficient conflict detection to allow more loops to be vectorized, supported by Knights Landing[3]
  • AVX-512 Exponential and Reciprocal Instructions (ER){{snd}} exponential and reciprocal operations designed to help implement transcendental operations, supported by Knights Landing[3]
  • AVX-512 Prefetch Instructions (PF){{snd}} new prefetch capabilities, supported by Knights Landing[3]
  • AVX-512 Vector Length Extensions (VL){{snd}} extends most AVX-512 operations to also operate on XMM (128-bit) and YMM (256-bit) registers (including XMM16-XMM31 and YMM16-YMM31 in x86-64 mode)[27]
  • AVX-512 Byte and Word Instructions (BW){{snd}} extends AVX-512 to cover 8-bit and 16-bit integer operations[22]
  • AVX-512 Doubleword and Quadword Instructions (DQ){{snd}} enhanced 32-bit and 64-bit integer operations[22]
  • AVX-512 Integer Fused Multiply Add (IFMA){{snd}} fused multiply add for 512-bit integers.[23]{{rp|746}}
  • AVX-512 Vector Byte Manipulation Instructions (VBMI) adds vector byte permutation instructions which are not present in AVX-512BW.
  • AVX-512 Vector Neural Network Instructions Word variable precision (4VNNIW){{snd}} vector instructions for deep learning.
  • AVX-512 Fused Multiply Accumulation Packed Single precision (4FMAPS){{snd}} vector instructions for deep learning.
  • VPOPCNTDQ{{snd}} count of bits set to 1.[24]
  • VPCLMULQDQ{{snd}} carry-less multiplication of quadwords.[24]
  • AVX-512 Vector Neural Network Instructions (VNNI){{snd}} vector instructions for deep learning.[24]
  • AVX-512 Galois Field New Instructions(GFNI){{snd}} vector instructions for calculating Galois Field.[24]
  • AVX-512 Vector AES instructions (VAES){{snd}} vector instructions for AES coding.[24]
  • AVX-512 Vector Byte Manipulation Instructions 2 (VBMI2){{snd}} byte/word load, store and concatenation with shift.[24]
  • AVX-512 Bit Algorithms (BITALG){{snd}} byte/word bit manipulation instructions expanding VPOPCNTDQ.[24]

Only the core extension AVX-512F (AVX-512 Foundation) is required by all implementations, though all current processors also support CD (conflict detection); computing coprocessors will additionally support ER, PF, 4VNNIW, 4FMAPS, and VPOPCNTDQ, while desktop processors will support VL, DQ, BW, IFMA, VBMI, VPOPCNTDQ, VPCLMULQDQ etc.

The updated SSE/AVX instructions in AVX-512F use the same mnemonics as AVX versions; they can operate on 512-bit ZMM registers, and will also support 128/256 bit XMM/YMM registers (with AVX-512VL) and byte, word, doubleword and quadword integer operands (with AVX-512BW/DQ and VBMI).[23]{{rp|23}}

CPUs with AVX-512

AVX-512 SubsetFCDERPF4FMAPS4VNNIWVLDQBWIFMAVBMIVBMI2VPOPCNTDQBITALGVNNIVPCLMULQDQGFNIVAES
Xeon Phi x200 (Knights Landing) processors (2016)colspan="2" rowspan="5" {{Yes}}colspan="2" {{Yes}}colspan="14" {{No}}
Knights Mill processors (2017)colspan="4" {{Yes}}colspan="6" {{No}}colspan="1" {{Yes}}colspan="5" {{No}}
Skylake-SP, Skylake-X processors (2017)colspan="4" rowspan="3" {{No}}colspan="3" {{Yes}}colspan="9" {{No}}
Cannon Lake processors (expected in 2018)colspan="5" {{Yes}}colspan="7" {{No}}
Ice Lake processorscolspan="12" {{Yes}}
[25]

Compilers supporting AVX-512

  • GCC 4.9 and newer[26]
  • Clang 3.9 and newer[27]
  • ICC 15.0.1 and newer[28]
  • Microsoft Visual Studio 2017 C++ Compiler[29]
  • Java 9[30]

Applications

  • Suitable for floating point-intensive calculations in multimedia, scientific and financial applications (AVX2 adds support for integer operations).
  • Increases parallelism and throughput in floating point SIMD calculations.
  • Reduces register load due to the non-destructive instructions.
  • Improves Linux RAID software performance (required AVX2, AVX is not sufficient)[31]

Software

  • Blender uses AVX2 in the render engine cycles.
  • OpenSSL uses AVX and AVX2 optimized cryptographic functions since version 1.0.2.[32]. This support is also present in various clones and forks, like LibreSSL
  • Prime95/MPrime, the software used for GIMPS, started using the AVX instructions since version 27.x.
  • dav1d AV1 decoder can use AVX2 on supported CPUs.[33]
  • dnetc, the software used by distributed.net, has an AVX2 core available for its RC5 project and will soon release one for its OGR-28 project.
  • Einstein@Home uses AVX in some of their distributed applications that search for gravitational waves.[34]
  • RPCS3, an open source PlayStation 3 emulator, uses AVX2 and AVX-512 instructions to emulate PS3 games.
  • Network Device Interface, NDI® is an IP video/audio protocol developed by NewTek for live broadcast production, uses AVX and AVX2 for increased performance.
  • Tensorflow since version 1.6 requires CPU supporting at least AVX.[35]
  • Xenia requires AVX instruction set in order to run.
  • x264 and x265 video encoders can use AVX2 or AVX-512 to speed up encoding.
  • Various CPU based cryptocurrency miners (like pooler's cpuminer for Bitcoin and Litecoin) use AVX and AVX2 for various crytography related routines, including SHA-256 and scrypt.
  • libsodium uses AVX in the implementation of scalar multiplication for Curve25519 and Ed25519 algorithms, AVX2 for BLAKE2b, Salsa20, ChaCha20, and AVX2 and AVX-512 in implementation of Argon2 algorithm.
  • libvpx open source reference implementation of VP8/VP9 encoder/decoder, uses AVX2 or AVX512 when available.
  • FFTW can utilize AVX, AVX2 and AVX-512 when available.
  • LLVMpipe a software OpenGL renderer in Mesa using Gallium and LLVM infrastructure, uses AVX2 when available.
  • glibc uses AVX2 (with FMA) for optimized implementation (i.e. expf, sinf, powf, atanf, atan2f) of various mathematical functions in libc.
  • Linux kernel uses can use AVX or AVX2, together with AES-NI as optimized implementation of AES-GCM cryptographic algorithm.
  • Linux kernel uses AVX or AVX2 when available, in optimized implementation of multiple other cryptographic ciphers: Camellia, CAST5, CAST6, Serpent, Twofish, MORUS-1280, and other primitives: Poly1305, SHA1, SHA256, SHA512, ChaCha20.
  • POCL, a portable Computing Language, that provides implementation of OpenCL, makes use of AVX, AVX2 and AVX512 when possible.
  • .NET Core and .NET Framework can utilize AVX through the System.Numerics.Vectors library.

See also

  • Memory Protection Extensions
  • Scalable Vector Extension for ARM - a new vector instruction set (supplementing VFP and NEON) similar to AVX-512, with some additional features.

References

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External links

  • [https://software.intel.com/sites/landingpage/IntrinsicsGuide/ Intel Intrinsics Guide]
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3 : X86 instructions|SIMD computing|Advanced Micro Devices technologies
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