词条 | AMD K5 |
释义 |
|name = K5 |image = AMD K5 PR166 Front.jpg |image_size = 200px |caption = An AMD K5 PR166 microprocessor |manufacturers = AMD |produced-start = March 27, 1996 (SSA/5) October 7, 1996 (5k86) |produced-end = |model = SSA/5 Series |model1 = 5k86 Series |transistors-nostep = 4.3M 500 nm |slowest = 75|slow-unit = MHz |fastest = 133|fast-unit = MHz |fsb-slowest = 50|fsb-slow-unit = MHz |fsb-fastest = 66|fsb-fast-unit = MHz |soldby = |sock1 = Socket 5 |sock2 = Socket 7 |brand1 = |arch = IA-32/x86 |microarch = K5 |cpuid = |code = |numcores = 1 |l1cache = 8 KB + 16 KB (data + instructions) |platform = Desktop, Embedded |predecessor = Am5x86 |successor = K6 }} The K5 is AMD's first x86 processor to be developed entirely in-house. Introduced in March 1996, its primary competition was Intel's Pentium microprocessor. The K5 was an ambitious design, closer to a Pentium Pro than a Pentium regarding technical solutions and internal architecture. However, the final product was closer to the Pentium regarding performance, although faster clock-for-clock compared to the Pentium. Technical detailsThe K5 was based upon an internal highly parallel 29k RISC processor architecture with an x86 decoding front-end. The K5 offered good x86 compatibility and the in-house-developed test suite proved invaluable on later projects. All models had 4.3 million transistors, with five integer units that could process instructions out of order and one floating-point unit. The branch target buffer was four times the size of the Pentium's and register renaming helped overcome register dependencies.[1] The chip's speculative execution of instructions reduced pipeline stalls. It had a 16 KB four-way set-associative instruction cache and an 8 KB data cache. The floating-point divide and square-root microcode were mechanically proven.[2] [3]The floating-point transcendental instructions were implemented in hardware and were faithful to true mathematical results for all operands.[4] PerformanceThe K5 project represented an early chance for AMD to take technical leadership from Intel. Although the chip addressed the right design concepts, the actual engineering implementation had its issues. The low clock rates were, in part, due to AMD's limitations as a "cutting edge" manufacturing company at the time, and in part due to the design itself, which had many levels of logic for the process technology of the day, hampering clock scaling. Additionally, while the K5's floating-point performance was regarded as superior to that of the Cyrix 6x86{{Clarify|date=March 2012}}, it was slower than that of the Pentium, although while offering more reliable transcendental function results. Because it was late to market and did not meet performance expectations, the K5 never gained the acceptance among large computer manufacturers that the Am486 and AMD K6 enjoyed. ModelsThere were two sets of K5 processors, internally called the SSA/5 and the 5k86, both released with the K5 label. The "SSA/5" had its branch-prediction unit disabled and additional internal waitstates added.[5] The "SSA/5" line ran from 75 to 100 MHz; the "5k86" line ran from 90 to 133 MHz. However, AMD used what it called a PR rating, or performance rating, to label the chips according to their equivalence to a Pentium of that clock speed. Thus, a 116 MHz chip from the second line was marketed as the "K5 PR166". Manufacturing delays caused the PR200's arrival to nearly align with the release of K6. Since AMD did not want the two chips competing, the K5-PR200 only arrived in small numbers. SSA/5
5k86
See also
References1. ^http://datasheets.chipdb.org/upload/Unzlbunzl/AMD/18522F%20AMD-K5.pdf 2. ^ J. Strother Moore, Thomas W. Lynch, Matt Kaufmann, "A Mechanically Checked Proof of the AMD5K86TM Floating-Point Division Program",IEEE Transactions on Computers,Volume 47 Issue 9, September 1998.Pages 913–926.IEEE Computer Society Washington, DC, USA. 3. ^David M. Russinoff,"A Mechanically Checked Proof of Correctness of the AMD K5 Floating Point Square Root Microcode",Formal Methods in System Design archive,Volume 14 Issue 1, January 1999.Pages 75–125.Kluwer Academic Publishers Hingham, MA, USA. 4. ^ T. Lynch, A. Ahmed, M. Schulte, T. Callaway, R. Tisdale"K5 Transcendental Functions",Proceedings of the 12th Symposium on Computer Arithmetic.19–21 July 1995.Pages 163–170.IEEE Computer Society Washington, DC, USA. 5. ^http://alasir.com/x86ref/index2.html Further reading
External links{{Commons category|AMD K5}}
2 : Advanced Micro Devices x86 microprocessors|Advanced Micro Devices microarchitectures |
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