1. Conversion Examples

2. See also

3. References

MyHDL^[1] is a Python based hardware description language (HDL).

Features of MyHDL include:

• The ability to generate VHDL and Verilog code from a MyHDL design.^[2]
• The ability to generate a testbench (Conversion of test benches^[3]) with test vectors in VHDL or Verilog, based on complex computations in Python.
• The ability to convert a lists of signals.^[4]
• The ability to convert output verification.^[5]
• The ability to do Co-simulation with Verilog.^[6]
• An advanced datatype system, independent of traditional datatypes. MyHDL's translator tool automatically writes conversion functions when the target language requires them.

MyHDL is developed by Jan Decaluwe.^[7]

Conversion Examples

Here, you can see some examples of conversions from MyHDL designs to VHDL and/or Verilog.^[8]

The example is a small combinatorial design, more specifically the binary to Gray code converter:

def bin2gray(B, G, width):

    B -- input intbv signal, binary encoded    G -- output intbv signal, gray encoded    width -- bit width

    @always_comb    def logic():        Bext = intbv(0)[width+1:]        Bext[:] = B        for i in range(width):            G.next[i] = Bext[i+1] ^ Bext[i]

You can create an instance and convert to Verilog and VHDL as follows:

width = 8

B = Signal(intbv(0)[width:])

G = Signal(intbv(0)[width:])

bin2gray_inst = toVerilog(bin2gray, B, G, width)

bin2gray_inst = toVHDL(bin2gray, B, G, width)

The generated Verilog code looks as follows:

module bin2gray (

    B,    G

);

input [7:0] B;

output [7:0] G;

reg [7:0] G;

always @(B) begin: BIN2GRAY_LOGIC

    integer i;    reg [9-1:0] Bext;    Bext = 9'h0;    Bext = B;    for (i=0; i<8; i=i+1) begin        G[i] <= (Bext[(i + 1)] ^ Bext[i]);    end

end

endmodule

The generated VHDL code looks as follows:

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

use std.textio.all;

use work.pck_myhdl_06.all;

entity bin2gray is

    port (        B: in unsigned(7 downto 0);        G: out unsigned(7 downto 0)    );

end entity bin2gray;

architecture MyHDL of bin2gray is

begin

BIN2GRAY_LOGIC: process (B) is

begin

    Bext := to_unsigned(0, 9);    Bext := resize(B, 9);    for i in 0 to 8-1 loop        G(i) <= (Bext((i + 1)) xor Bext(i));    end loop;

end process BIN2GRAY_LOGIC;

end architecture MyHDL;

See also

• Comparison of Free EDA software
• Comparison of EDA Software
• Electronic design automation (EDA)

References

• Lucas Galdino
• Lucas Galdino De Paiva
• Lucas Galdino de Paiva
• Lucas García Simón
• Lucas Gatti
• Lucas Gaúcho
• Lucas Gilbertson
• Lucas Glacier
• Lucas Gonzalez Amorosino
• Lucas Gonzalez, Argentina
• Lucas González Amorosino
• Lucas González, Argentina
• Lucas González (localidad)
• Lucas Gottesman
• Lucas Green, Lancashire
• Lucas Green, Surrey
• Lucas Haedo
• Lucas Harrell
• Lucas Hay
• Lucas Heights Reactor
• Lucas Hendley Glover
• Lucashof
• Lucas Hoving
• Lucas Hradecky
• Lucas Hunt