词条 | Fast interrupt request |
释义 |
An FIQ takes priority over an IRQ in an ARM system. Also, only one FIQ source at a time is supported. This helps reduce interrupt latency as the interrupt service routine can be executed directly without determining the source of the interrupt. A context save is not required for servicing an FIQ since it has its own set of banked registers. This reduces the overhead of context switching. References1. ^https://infocenter.arm.com/ {{tech-stub}}2. ^https://www.marilynwolf.us/CaC3e/ 1 : Interrupts |
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