1. Rationale

2. Overview
    HSA memory model  HSA dispatcher and run-time  Block diagrams 

3. Software support{{Anchor|AMDKFD|HQ|HMM}}

4. Hardware support
    AMD  ARM 

5. See also

6. References

7. External links

CUDA and OpenCL as well as most other fairly advanced programming languages can use HSA to increase their execution performance.^[5] Heterogeneous computing is widely used in system-on-chip devices such as tablets, smartphones, other mobile devices, and video game consoles.^[6] HSA allows programs to use the graphics processor for floating point calculations without separate memory or scheduling.^[7]

Rationale

The rationale behind HSA is to ease the burden on programmers when offloading calculations to the GPU. Originally driven solely by AMD and called the FSA, the idea was extended to encompass processing units other than GPUs, such as other manufacturers' DSPs, as well.

Modern GPUs are very well suited to perform single instruction, multiple data (SIMD) and single instruction, multiple threads (SIMT), while modern CPUs are still being optimized for branching. etc.

Overview

Originally introduced by embedded systems such as the Cell Broadband Engine, sharing system memory directly between multiple system actors makes heterogeneous computing more mainstream. Heterogeneous computing itself refers to systems that contain multiple processing units{{snd}} central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), or any type of application-specific integrated circuits (ASICs). The system architecture allows any accelerator, for instance a graphics processor, to operate at the same processing level as the system's CPU.

Among its main features, HSA defines a unified virtual address space for compute devices: where GPUs traditionally have their own memory, separate from the main (CPU) memory, HSA requires these devices to share page tables so that devices can exchange data by sharing pointers. This is to be supported by custom memory management units.^[2]{{rp|6–7}} To render interoperability possible and also to ease various aspects of programming, HSA is intended to be ISA-agnostic for both CPUs and accelerators, and to support high-level programming languages.

So far, the HSA specifications cover:

===HSA Intermediate Layer===

HSA Intermediate Layer (HSAIL), a virtual instruction set for parallel programs

• similar{{according to whom|date=May 2015}} to LLVM Intermediate Representation and SPIR (used by OpenCL and Vulkan)
• finalized to a specific instruction set by a JIT compiler
• make late decisions on which core(s) should run a task
• explicitly parallel
• supports exceptions, virtual functions and other high-level features
• debugging support

HSA memory model

• compatible with C++11, OpenCL, Java and .NET memory models
• relaxed consistency
• designed to support both managed languages (e.g. Java) and unmanaged languages (e.g. C)
• will make it much easier to develop 3rd-party compilers for a wide range of heterogeneous products programmed in Fortran, C++, C++ AMP, Java, et al.

HSA dispatcher and run-time

• designed to enable heterogeneous task queueing: a work queue per core, distribution of work into queues, load balancing by work stealing
• any core can schedule work for any other, including itself
• significant reduction of overhead of scheduling work for a core

Mobile devices are one of the HSA's application areas, in which it yields improved power efficiency.^[6]

Block diagrams

The block diagrams below provide high-level illustrations of how HSA operates and how it compares to traditional architectures.

Software support{{Anchor|AMDKFD|HQ|HMM}}

Some of the HSA-specific features implemented in the hardware need to be supported by the operating system kernel and specific device drivers. For example, support for AMD Radeon and AMD FirePro graphics cards, and APUs based on Graphics Core Next (GCN), was merged into version 3.19 of the Linux kernel mainline, released on February 8, 2015.^[10] Programs do not interact directly with {{Mono|amdkfd}}, but queue their jobs utilizing the HSA runtime.^[11] This very first implementation, known as {{Mono|amdkfd}}, focuses on "Kaveri" or "Berlin" APUs and works alongside the existing Radeon kernel graphics driver.

Additionally, {{Mono|amdkfd}} supports heterogeneous queuing (HQ), which aims to simplify the distribution of computational jobs among multiple CPUs and GPUs from the programmer's perspective. Support for heterogeneous memory management (HMM), suited only for graphics hardware featuring version 2 of the AMD's IOMMU, was accepted into the Linux kernel mainline version 4.14.^[12]

Integrated support for HSA platforms has been announced for the "Sumatra" release of OpenJDK, due in 2015.^[13]

Hardware support

AMD

Post-2015 Carrizo and Bristol Ridge APUs also include the version 2 IOMMU functionality for the integrated GPU.{{Citation needed|date=June 2016}}

ARM

ARM's Bifrost microarchitecture, as implemented in the Mali-G71,^[16] is fully compliant with the HSA 1.1 hardware specifications. {{As of|2016|6}}, ARM has not announced software support that would use this hardware feature.

See also

• General-purpose computing on graphics processing units (GPGPU)
• Non-Uniform Memory Access (NUMA)
• OpenMP
• Shared memory
• Zero-copy

References

External links

• {{YouTube|id=ln8JpfaLvbM|title=HSA Heterogeneous System Architecture Overview}} by Vinod Tipparaju at SC13 in November 2013
• HSA and the software ecosystem
• 2012 – HSA by Michael Houston

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