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词条 List of ARM microarchitectures
释义

  1. ARM cores

     Designed by ARM  Designed by third parties 

  2. ARM core timeline

  3. See also

  4. References

  5. Further reading

{{Redirect|ARM8|the ARMv8-A architecture|ARMv8-A|the ARMv8-R architecture|ARMv8-R}}{{Use dmy dates|date=February 2015}}

This is a list of microarchitectures based on the ARM family of instruction sets designed by ARM Holdings and 3rd parties, sorted by version of the ARM instruction set, release and name. ARM provides a summary of the numerous vendors who implement ARM cores in their design.[1] Keil also provides a somewhat newer summary of vendors of ARM based processors.[2] ARM further provides a chart[3] displaying an overview of the ARM processor lineup with performance and functionality versus capabilities for the more recent ARM core families.

ARM cores

Designed by ARM

ARM family ARM architecture ARM core Feature Cache (I / D), MMU Typical MIPS @ MHz Reference
ARM1ARMv1ARM1First implementationNone
ARM2ARMv2ARM2ARMv2 added the MUL (multiply) instructionNone4 MIPS @ 8 MHz
0.33 DMIPS/MHz
ARMv2aARM250Integrated MEMC (MMU), graphics and I/O processor. ARMv2a added the SWP and SWPB (swap) instructionsNone, MEMC1a7 MIPS @ 12 MHz
ARM3ARMv2aARM3First integrated memory cache4 KB unified12 MIPS @ 25 MHz
0.50 DMIPS/MHz
ARM6ARMv3ARM60ARMv3 first to support 32-bit memory address space (previously 26-bit).
ARMv3M first added long multiply instructions (32x32=64).		None10 MIPS @ 12 MHz
ARM600As ARM60, cache and coprocessor bus (for FPA10 floating-point unit)4 KB unified28 MIPS @ 33 MHz
ARM610As ARM60, cache, no coprocessor bus4 KB unified17 MIPS @ 20 MHz
0.65 DMIPS/MHz		[4]
ARM7ARMv3ARM7008 KB unified40 MHz
ARM710As ARM700, no coprocessor bus8 KB unified40 MHz[5]
ARM710aAs ARM7108 KB unified40 MHz
0.68 DMIPS/MHz
ARM7TARMv4TARM7TDMI(-S)3-stage pipeline, Thumb, ARMv4 first to drop legacy ARM 26-bit addressingNone15 MIPS @ 16.8 MHz
63 DMIPS @ 70 MHz
ARM710TAs ARM7TDMI, cache8 KB unified, MMU36 MIPS @ 40 MHz
ARM720TAs ARM7TDMI, cache8 KB unified, MMU with FCSE (Fast Context Switch Extension)60 MIPS @ 59.8 MHz
ARM740TAs ARM7TDMI, cacheMPU
ARM7EJARMv5TEJARM7EJ-S5-stage pipeline, Thumb, Jazelle DBX, enhanced DSP instructionsNone
ARM8ARMv4ARM8105-stage pipeline, static branch prediction, double-bandwidth memory 8 KB unified, MMU 84 MIPS @ 72 MHz
1.16 DMIPS/MHz		[6][7]
ARM9TARMv4TARM9TDMI5-stage pipeline, ThumbNone
ARM920TAs ARM9TDMI, cache16 KB / 16 KB, MMU with FCSE (Fast Context Switch Extension)200 MIPS @ 180 MHz[8]
ARM922TAs ARM9TDMI, caches8 KB / 8 KB, MMU
ARM940TAs ARM9TDMI, caches4 KB / 4 KB, MPU
ARM9EARMv5TEARM946E-SThumb, enhanced DSP instructions, cachesVariable, tightly coupled memories, MPU
ARM966E-SThumb, enhanced DSP instructionsNo cache, TCMs
ARM968E-SAs ARM966E-SNo cache, TCMs
ARMv5TEJARM926EJ-SThumb, Jazelle DBX, enhanced DSP instructionsVariable, TCMs, MMU220 MIPS @ 200 MHz
ARMv5TEARM996HSClockless processor, as ARM966E-SNo caches, TCMs, MPU
ARM10EARMv5TEARM1020E6-stage pipeline, Thumb, enhanced DSP instructions, (VFP)32 KB / 32 KB, MMU
ARM1022EAs ARM1020E16 KB / 16 KB, MMU
ARMv5TEJARM1026EJ-SThumb, Jazelle DBX, enhanced DSP instructions, (VFP)Variable, MMU or MPU
ARM11ARMv6ARM1136J(F)-S8-stage pipeline, SIMD, Thumb, Jazelle DBX, (VFP), enhanced DSP instructions, unaligned memory accessVariable, MMU740 @ 532–665 MHz (i.MX31 SoC), 400–528 MHz[9]
ARMv6T2ARM1156T2(F)-S9-stage pipeline, SIMD, Thumb-2, (VFP), enhanced DSP instructionsVariable, MPU[10]
ARMv6ZARM1176JZ(F)-SAs ARM1136EJ(F)-SVariable, MMU + TrustZone965 DMIPS @ 772 MHz, up to 2,600 DMIPS with four processors[11]
ARMv6KARM11MPCoreAs ARM1136EJ(F)-S, 1–4 core SMPVariable, MMU
SecurCore ARMv6-M SC000 0.9 DMIPS/MHz
ARMv4T SC100
ARMv7-M SC300 1.25 DMIPS/MHz
Cortex-MARMv6-MCortex-M0[12]Microcontroller profile, most Thumb + some Thumb-2,[13] hardware multiply instruction (optional small), optional system timer, optional bit-banding memoryOptional cache, no TCM, no MPU0.84 DMIPS/MHz
Cortex-M0+[14]Microcontroller profile, most Thumb + some Thumb-2,[13] hardware multiply instruction (optional small), optional system timer, optional bit-banding memoryOptional cache, no TCM, optional MPU with 8 regions0.93 DMIPS/MHz
Cortex-M1[15]Microcontroller profile, most Thumb + some Thumb-2,[13] hardware multiply instruction (optional small), OS option adds SVC / banked stack pointer, optional system timer, no bit-banding memoryOptional cache, 0–1024 KB I-TCM, 0–1024 KB D-TCM, no MPU136 DMIPS @ 170 MHz,[16] (0.8 DMIPS/MHz FPGA-dependent)[17]
ARMv7-MCortex-M3[18]Microcontroller profile, Thumb / Thumb-2, hardware multiply and divide instructions, optional bit-banding memoryOptional cache, no TCM, optional MPU with 8 regions1.25 DMIPS/MHz
ARMv7E-MCortex-M4[19]Microcontroller profile, Thumb / Thumb-2 / DSP / optional VFPv4-SP single-precision FPU, hardware multiply and divide instructions, optional bit-banding memoryOptional cache, no TCM, optional MPU with 8 regions1.25 DMIPS/MHz (1.27 w/FPU)
Cortex-M7[20]Microcontroller profile, Thumb / Thumb-2 / DSP / optional VFPv5 single and double precision FPU, hardware multiply and divide instructions0−64 KB I-cache, 0−64 KB D-cache, 0–16 MB I-TCM, 0–16 MB D-TCM (all these w/optional ECC), optional MPU with 8 or 16 regions2.14 DMIPS/MHz
Cortex-RARMv7-RCortex-R4[21]Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running lockstep with fault logic0–64 KB / 0–64 KB, 0–2 of 0–8 MB TCM, opt. MPU with 8/12 regions1.67 DMIPS/MHz[22]
Cortex-R5[23]Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU and precision, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running lock-step with fault logic / optional as 2 independent cores, low-latency peripheral port (LLPP), accelerator coherency port (ACP)[24]0–64 KB / 0–64 KB, 0–2 of 0–8 MB TCM, opt. MPU with 12/16 regions1.67 DMIPS/MHz[22]
Cortex-R7[25]Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU and precision, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 11-stage pipeline dual-core running lock-step with fault logic / out-of-order execution / dynamic register renaming / optional as 2 independent cores, low-latency peripheral port (LLPP), ACP[24]0–64 KB / 0–64 KB, ? of 0–128 KB TCM, opt. MPU with 16 regions2.50 DMIPS/MHz[22]
Cortex-R8[26]TBDTBD2.50 DMIPS/MHz[22]
ARMv8-RCortex-R52[27]TBDTBD2.16 DMIPS/MHz[28]
Cortex-A
(32-bit)		ARMv7-A Cortex-A5[29]Application profile, ARM / Thumb / Thumb-2 / DSP / SIMD / Optional VFPv4-D16 FPU / Optional NEON / Jazelle RCT and DBX, 1–4 cores / optional MPCore, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)4−64 KB / 4−64 KB L1, MMU + TrustZone1.57 DMIPS/MHz per core
Cortex-A7[30]Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4 FPU / NEON / Jazelle RCT and DBX / Hardware virtualization, in-order execution, superscalar, 1–4 SMP cores, MPCore, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP, architecture and feature set are identical to A15, 8–10 stage pipeline, low-power design[31]8−64 KB / 8−64 KB L1, 0–1 MB L2, MMU + TrustZone1.9 DMIPS/MHz per core
Cortex-A8[32]Application profile, ARM / Thumb / Thumb-2 / VFPv3 FPU / NEON / Jazelle RCT and DAC, 13-stage superscalar pipeline16–32 KB / 16–32 KB L1, 0–1 MB L2 opt. ECC, MMU + TrustZoneUp to 2000 (2.0 DMIPS/MHz in speed from 600 MHz to greater than 1 GHz)
Cortex-A9[33]Application profile, ARM / Thumb / Thumb-2 / DSP / Optional VFPv3 FPU / Optional NEON / Jazelle RCT and DBX, out-of-order speculative issue superscalar, 1–4 SMP cores, MPCore, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)16–64 KB / 16–64 KB L1, 0–8 MB L2 opt. parity, MMU + TrustZone2.5 DMIPS/MHz per core, 10,000 DMIPS @ 2 GHz on Performance Optimized TSMC 40G (dual-core)
Cortex-A12[34]Application profile, ARM / Thumb-2 / DSP / VFPv4 FPU / NEON / Hardware virtualization, out-of-order speculative issue superscalar, 1–4 SMP cores, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)32−64 KB3.0 DMIPS/MHz per core
Cortex-A15[35]Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4 FPU / NEON / integer divide / fused MAC / Jazelle RCT / hardware virtualization, out-of-order speculative issue superscalar, 1–4 SMP cores, MPCore, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP, 15-24 stage pipeline[31]32 KB w/parity / 32 KB w/ECC L1, 0–4 MB L2, L2 has ECC, MMU + TrustZoneAt least 3.5 DMIPS/MHz per core (up to 4.01 DMIPS/MHz depending on implementation)[36]
Cortex-A17[37]Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4 FPU / NEON / integer divide / fused MAC / Jazelle RCT / hardware virtualization, out-of-order speculative issue superscalar, 1–4 SMP cores, MPCore, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP32 KB L1, 256 KB–8 MB L2 w/optional ECC2.8 DMIPS/MHz
ARMv8-ACortex-A32[38]Application profile, AArch32, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, dual issue, in-order pipeline8–64 KB w/optional parity / 8−64 KB w/optional ECC L1 per core, 128 KB–1 MB L2 w/optional ECC shared
Cortex-A
(64-bit)		ARMv8-ACortex-A35[39]Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, dual issue, in-order pipeline 8−64 KB w/parity / 8−64 KB w/ECC L1 per core, 128 KB–1 MB L2 shared, 40-bit physical addresses1.78 DMIPS/MHz
Cortex-A53[40] Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, dual issue, in-order pipeline 8−64 KB w/parity / 8−64 KB w/ECC L1 per core, 128 KB–2 MB L2 shared, 40-bit physical addresses 2.3 DMIPS/MHz
Cortex-A57[41] Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 3-way superscalar, deeply out-of-order pipeline48 KB w/DED parity / 32 KB w/ECC L1 per core; 512 KB–2 MB L2 shared w/ECC; 44-bit physical addresses4.1 - 4.5 DMIPS/MHz[42][43]
Cortex-A72[44] Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 3-way superscalar, deeply out-of-order pipeline48 KB w/DED parity / 32 KB w/ECC L1 per core; 512 KB–2 MB L2 shared w/ECC; 44-bit physical addresses4.7 DMIPS/MHz
Cortex-A73[45] Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-way superscalar, deeply out-of-order pipeline64 KB / 32−64 KB L1 per core, 256 KB–8 MB L2 shared w/ optional ECC, 44-bit physical addresses4.8 DMIPS/MHz[46]
ARMv8.2-ACortex-A55[47]Application profile, AArch32 and AArch64, 1–8 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, triple issue, in-order pipeline[48]64 / 64 kB L1, 256 kB L2 per core, 4 MB L3 shared
Cortex-A75[49]Application profile, AArch32 and AArch64, 1–8 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 3-way superscalar, deeply out-of-order pipeline[50]64 / 64 kB L1, 512 kB L2 per core, 4 MB L3 shared
Cortex-A76[51] Application profile, AArch32 (non-privileged level or EL0 only) and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 4-way superscalar, 8-way issue, deeply out-of-order pipeline[52]64 / 64 kB L1, 256−512 kB L2 per core, 512 kB−4 MB L3 shared
ARM family ARM architecture ARM core Feature Cache (I / D), MMU Typical MIPS @ MHz Reference

As Dhrystone is a synthetic benchmark developed in 1980s, it is no longer representative of prevailing workloads{{snd}}use with caution.

Designed by third parties

These cores implement the ARM instruction set, and were developed independently by companies with an architectural license from ARM.

Core Family Instruction set Microarchitecture Feature Cache (I / D), MMU Typical MIPS @ MHz
StrongARM
(Digital)		ARMv4 SA-110 5-stage pipeline 16 KB / 16 KB, MMU 100–233 MHz
1.0 DMIPS/MHz
SA-1100 derivative of the SA-110 16 KB / 8 KB, MMU
Faraday[53]
(Faraday Technology)		ARMv4 FA510 6-stage pipeline Up to 32 KB / 32 KB cache, MPU 1.26 DMIPS/MHz
100–200 MHz
FA526 Up to 32 KB / 32 KB cache, MMU 1.26 MIPS/MHz
166–300 MHz
FA626 8-stage pipeline 32 KB / 32 KB cache, MMU 1.35 DMIPS/MHz
500 MHz
ARMv5TE FA606TE 5-stage pipeline No cache, no MMU 1.22 DMIPS/MHz
200 MHz
FA626TE 8-stage pipeline32 KB / 32 KB cache, MMU 1.43 MIPS/MHz
800 MHz
FMP626TE 8-stage pipeline, SMP 1.43 MIPS/MHz
500 MHz
FA726TE 13 stage pipeline, dual issue 2.4 DMIPS/MHz
1000 MHz
XScale
(Intel / Marvell)		ARMv5TE XScale 7-stage pipeline, Thumb, enhanced DSP instructions 32 KB / 32 KB, MMU 133–400 MHz
Bulverde Wireless MMX, wireless SpeedStep added 32 KB / 32 KB, MMU 312–624 MHz
Monahans[54] Wireless MMX2 added 32 KB / 32 KB L1, optional L2 cache up to 512 KB, MMU Up to 1.25 GHz
Sheeva
(Marvell)		ARMv5 Feroceon 5–8 stage pipeline, single-issue 16 KB / 16 KB, MMU 600–2000 MHz
Jolteon 5–8 stage pipeline, dual-issue 32 KB / 32 KB, MMU
PJ1 (Mohawk) 5–8 stage pipeline, single-issue, Wireless MMX2 32 KB / 32 KB, MMU 1.46 DMIPS/MHz
1.06 GHz
ARMv6 / ARMv7-A PJ4 6–9 stage pipeline, dual-issue, Wireless MMX2, SMP 32 KB / 32 KB, MMU 2.41 DMIPS/MHz
1.6 GHz
Snapdragon
(Qualcomm)		ARMv7-A Scorpion[55] 1 or 2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv3 FPU / NEON (128-bit wide)256 KB L2 per core2.1 DMIPS/MHz per core
Krait[55] 1, 2, or 4 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON (128-bit wide)4 KB / 4 KB L0, 16 KB / 16 KB L1, 512 KB L2 per core3.3 DMIPS/MHz per core
ARMv8-A Kryo[56] 4 cores. ? Up to 2.2 GHz

(6.3 DMIPS/MHz)

Ax
(Apple)		ARMv7-A Swift[57] 2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEONL1: 32 KB / 32 KB, L2: 1 MB3.5 DMIPS/MHz per core
ARMv8-A Cyclone[58] 2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON / TrustZone / AArch64 L1: 64 KB / 64 KB, L2: 1 MB, L3: 4 MB 1.3–1.4 GHz
ARMv8-A Typhoon[58][59] 2 or 3 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON / TrustZone / AArch64 L1: 64 KB / 64 KB, L2: 1 or 2 MB, L3: 4 MB 1.4−1.5 GHz
ARMv8-A Twister[60] 2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON / TrustZone / AArch64 L1: 64 KB / 64 KB, L2: 2 MB, L3: 4 MB or 0 MB 1.85 or 2.26 GHz
ARMv8-A Hurricane[61] 2 or 3 cores. AArch64, 6-decode, 6-issue, 9-wide, superscalar, out-of-order L1: 64 KB / 64 KB, L2: 3 or 8 MB, L3: 4 or 0 MB 2.34 or 2.38 GHz
ARMv8-A Monsoon[62] 2 cores. AArch64, 7-decode, 6-issue, 10-wide, superscalar, out-of-order L1: 64 KB / 64 KB, L2: 8MB, L3: none 2.39 GHz
ARMv8.3-A Vortex[63] 2 or 4 cores. AArch64, 7-decode, 6-issue, 10-wide, superscalar, out-of-order L1: 128 KB / 128 KB, L2: 8MB, L3: None 2.5 GHz
X-Gene
(Applied Micro)		 ARMv8-A X-Gene 64-bit, quad issue, SMP, 64 cores[64] Cache, MMU, virtualization 3 GHz (4.2 DMIPS/MHz per core)
Denver
(Nvidia)		 ARMv8-A Denver[65][66] 2 cores. AArch64, 7-wide superscalar, in-order, dynamic code optimization, 128 MB optimization cache,
Denver1: 28nm, Denver2:16nm 		128 KB I-cache / 64 KB D-cache Up to 2.5 GHz
Carmel
(Nvidia)		 ARMv8(t.b.d.) Carmel[67][68] 2 cores. AArch64, 10-wide superscalar, in-order, dynamic code optimization, ? MB optimization cache,
functional safety, dual execution, parity & ECC 		? KB I-cache / ? KB D-cache Up to ? GHz
ThunderX
(Cavium)		 ARMv8-A ThunderX 64-bit, with two models with 8–16 or 24–48 cores (×2 w/two chips) ? Up to 2.2 GHz
K12
(AMD)		 ARMv8-A K12[69] ? ? ?
Exynos
(Samsung)		 ARMv8-A M1/M2 ("Mongoose")[70] 4 cores. AArch64, 4-wide, quad-issue, superscalar, out-of-order 64 KB I-cache / 32 KB D-cache, L2: 16-way shared 2 MB 5.1 DMIPS/MHz

(2.6 GHz)

ARMv8-A M3 ("Meerkat")[71] 4 cores, AArch64, 6-decode, 6-issue, 6-wide. superscalar, out-of-order 64 KB I-cache / 32 KB D-cache, L2: 8-way private 512 KB, L3: 16-way shared 4 MB ?

ARM core timeline

The following table lists each core by the year it was announced.[72][73] Cores before ARM7 are not included.

>
YearClassic coresCortex cores
ARM7 ARM8 ARM9 ARM10 ARM11 Microcontroller Real-time Application
(32-bit) 		Application
(64-bit)
1993 ARM700
1994 ARM710
ARM7DI
ARM7TDMI
1995 ARM710a
1996 ARM810
1997 ARM710T
ARM720T
ARM740T
1998 ARM9TDMI
ARM940T
1999 ARM9E-S
ARM966E-S
2000 ARM920T
ARM922T
ARM946E-S 		ARM1020T
2001 ARM7TDMI-S
ARM7EJ-S 		ARM9EJ-S
ARM926EJ-S 		ARM1020E
ARM1022E
2002 ARM1026EJ-S ARM1136J(F)-S
2003 ARM968E-S ARM1156T2(F)-S
ARM1176JZ(F)-S
2004 Cortex-M3
2005 ARM11MPCore Cortex-A8
2006 ARM996HS
2007 Cortex-M1 Cortex-A9
2008
2009 Cortex-M0 Cortex-A5
2010 Cortex-M4(F) Cortex-A15
2011 Cortex-R4
Cortex-R5
Cortex-R7 		Cortex-A7
2012 Cortex-M0+ Cortex-A53
Cortex-A57
2013 Cortex-A12
2014 Cortex-M7(F) Cortex-A17
2015 Cortex-A35
Cortex-A72
2016 Cortex-M23
Cortex-M33(F) 		Cortex-R8
Cortex-R52 		Cortex-A32 Cortex-A73
2017 Cortex-A55
Cortex-A75
2018 Cortex-M35P Cortex-A76

See also

{{Portal|Computer science|Electronics}}
  • Comparison of ARMv7-A cores
  • Comparison of ARMv8-A cores
  • List of applications of ARM cores
  • ARM architecture

References

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29. ^Cortex-A5 Specification Summary; ARM Holdings.
30. ^Cortex-A7 Specification Summary; ARM Holdings.
31. ^1 {{cite news|url=https://www.theregister.co.uk/2011/10/20/details_on_big_little_processing/ |title=Deep inside ARM's new Intel killer |publisher=The Register |date=20 October 2011}}
32. ^Cortex-A8 Specification Summary; ARM Holdings.
33. ^Cortex-A9 Specification Summary; ARM Holdings.
34. ^Cortex-A12 Summary; ARM Holdings.
35. ^Cortex-A15 Specification Summary; ARM Holdings.
36. ^Exclusive : ARM Cortex-A15 "40 Per Cent" Faster Than Cortex-A9 | ITProPortal.com
37. ^Cortex-A17 Specification Summary; ARM Holdings.
38. ^{{cite web | url=http://www.arm.com/products/processors/cortex-a/cortex-a32-processor.php | title=Cortex-A32 Processor | publisher=ARM Holdings | accessdate=18 May 2016}}
39. ^{{cite web | url=http://www.arm.com/products/processors/cortex-a/cortex-a35-processor.php | title=Cortex-A35 Processor | publisher=ARM Holdings | accessdate=18 May 2016}}
40. ^{{cite web | url=http://www.arm.com/products/processors/cortex-a50/cortex-a53-processor.php | title=Cortex-A53 Processor | publisher=ARM Holdings | accessdate=13 October 2012}}
41. ^{{cite web | url=http://www.arm.com/products/processors/cortex-a50/cortex-a57-processor.php | title=Cortex-A57 Processor | publisher=ARM Holdings | accessdate=13 October 2012}}
42. ^{{cite web | url=http://www.bitkistl.com/2015/03/cortex-ax-vs-performnace.html | title=Cortex-Ax vs performance | accessdate=5 May 2017}}
43. ^{{cite web | url=http://www.cnx-software.com/2015/04/09/relative-performance-of-arm-cortex-a-32-bit-and-64-bit-cores | title=Relative Performance of ARM Cortex-A 32-bit and 64-bit Cores | accessdate=5 May 2017}}
44. ^{{cite web | url=http://www.arm.com/products/processors/cortex-a/cortex-a72-processor.php | title=Cortex-A72 Processor | publisher=ARM Holdings | accessdate=3 February 2015}}
45. ^{{cite web | url=http://www.arm.com/products/processors/cortex-a/cortex-a73-processor.php | title=Cortex-A73 Processor | publisher=ARM Holdings | accessdate=2 June 2016}}
46. ^{{cite web | url=http://www.bitkistl.com/2015/03/cortex-ax-vs-performnace.html | title=Cortex-Ax vs performance | accessdate=5 May 2017}}
47. ^{{Cite web|url=https://developer.arm.com/products/processors/cortex-a/cortex-a55|title=Cortex-A55 – Arm Developer|publisher=Arm Ltd.|website=ARM Developer|language=en|access-date=2017-11-27}}
48. ^{{Cite web|url=https://nl.hardware.info/reviews/7394/4/preview-arms-nieuwe-cpu--en-gpu-architecturen-cortex-a55-efficientie|title=Hardware.Info Nederland|website=nl.hardware.info|language=nl|access-date=2017-11-27}}
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52. ^{{Cite web|url=https://anandtech.com/show/12785/arm-cortex-a76-cpu-unveiled-7nm-powerhouse/2|title=Arm's Cortex-A76 CPU Unveiled: Taking Aim at the Top for 7nm|website=AnandTech|access-date=2018-11-15}}
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55. ^1 Qualcomm's New Snapdragon S4: MSM8960 & Krait Architecture Explored; Anandtech.
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57. ^{{cite web|url=http://www.anandtech.com/show/6292/iphone-5-a6-not-a15-custom-core|title=The iPhone 5's A6 SoC: Not A15 or A9, a Custom Apple Core Instead|publisher=AnandTech|date=15 September 2012|accessdate=15 September 2012|first=Anand|last=Lal Shimpi}}
58. ^1 {{cite web|url=http://www.anandtech.com/show/8716/apple-a8xs-gpu-gxa6850-even-better-than-i-thought|title=Apple A8X's GPU - GAX6850, Even Better Than I Thought|first=Ryan|last=Smith|date=November 11, 2014|publisher=Anandtech}}
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60. ^{{cite web |url=http://www.anandtech.com/show/9662/iphone-6s-and-iphone-6s-plus-preliminary-results |title=iPhone 6s and iPhone 6s Plus Preliminary Results |first=Joshua |last=Ho |date=September 28, 2015 |publisher=Anandtech |accessdate=December 18, 2015}}
61. ^{{cite web |url=http://www.anandtech.com/show/10685/the-iphone-7-and-iphone-7-plus-review |title=The iPhone 7 and iPhone 7 Plus Review |first=Joshua |last=Ho |date=September 28, 2015 |publisher=Anandtech |accessdate=September 14, 2017}}
62. ^{{cite web |url=https://en.wikichip.org/wiki/apple/ax/a11 |title=A11 Bionic - Apple |publisher=WikiChip |accessdate=February 1, 2019}}
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64. ^http://www.pcworld.com/article/2464600/appliedmicros-64core-chip-could-spark-off-arm-core-war.html
65. ^http://www.anandtech.com/Gallery/Album/3847
66. ^http://blogs.nvidia.com/blog/2014/08/11/tegra-k1-denver-64-bit-for-android/
67. ^https://www.golem.de/news/nvidia-drive-xavier-fuer-autonome-autos-wird-ausgeliefert-1801-132035.html
68. ^https://wccftech.com/nvidia-drive-xavier-soc-detailed/
69. ^http://www.anandtech.com/show/7990/amd-announces-k12-core-custom-64bit-arm-design-in-2016
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71. ^{{cite web|url=https://www.anandtech.com/show/13199/hot-chips-2018-samsungs-exynosm3-cpu-architecture-deep-dive|title=Hot Chips 2018: Samsung’s Exynos-M3 CPU Architecture Deep Dive |work=AnandTech}}
72. ^ARM Company Milestones.
73. ^ARM Press Releases.

Further reading

{{See also|ARM Cortex-M#Further reading|l1=List of books about ARM Cortex-M}}{{Application ARM-based chips}}{{Embedded ARM-based chips}}{{Classic ARM-based chips}}{{DEFAULTSORT:ARM microarchitectures}}

4 : Lists of microprocessors|ARM architecture|ARM cores|Microarchitectures
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