| 释义 |
- Operation
- {{anchor|STSCL}}Ultra low power
- See also
- References
- External links
Current mode logic (CML), or source-coupled logic (SCL), is a differential digital logic family intended to transmit data at speeds between 312.5 Mbit/s and 3.125 Gbit/s across standard printed circuit boards.[1]The transmission is point-to-point, unidirectional, and is usually terminated at the destination with 50 Ω resistors to Vcc on both differential lines. CML is frequently used in interfaces to fiber optic components. CML signals have also been found useful for connections between modules. CML is the physical layer used in DVI and HDMI video links, the interfaces between a display controller and a monitor.[2] In addition CML has been widely used in high-speed integrated systems, such as telecommunication systems such as: serial data transceivers, frequency synthesizers. OperationThe fast operation of CML circuits is mainly due to their lower output voltage swing compared to the static CMOS circuits as well as the very fast current switching taking place at the input differential pair transistors. One of the primary requirements of a current-mode logic circuit is that the current bias transistor must remain in the saturation region in order to maintain a constant current. {{anchor|STSCL}}Ultra low powerRecently, CML has been used in ultra-low power applications. Studies show that while the leakage current in conventional static CMOS circuits is becoming a major challenge in lowering the energy dissipation, good control of CML current consumption makes them a very good candidate for extremely low power use. Called subthreshold CML or subthreshold source coupled logic (STSCL), See also - Low-voltage differential signaling (LVDS) A differential standard used primarily for signals between modules.
- Positive-referenced emitter-coupled logic, a differential signalling standard for high speed inter-module communications
- Display controller – IC that produces the signal
References1. ^Serial Interface for Data Converters, JEDEC standard JESD204, April 2006
2. ^{{cite web|url=http://www.bicsi.org/pdf/Regions/charlotte_se_4_11/Understanding%20DVI-D,%20HDMI%20and%20Display%20Port%20Signals.pdf|title=Understanding DVI‐D, HDMI And DisplayPort Signals|accessdate=2013-10-30}}
3. ^1 {{cite book |author-first1=Armin |author-last1=Tajalli |author-first2=Yusuf |author-last2=Leblebici |title=Extreme low-power mixed signal IC design: subthreshold source-coupled circuits |publisher=Springer, New York |isbn=978-1-4419-6477-9}}
4. ^1 {{cite book |title=Ultra-Low-Voltage Design of Energy-Efficient Digital Circuits |author-first1=Nele |author-last1=Reynders |author-first2=Wim |author-last2=Dehaene |series=Analog Circuits And Signal Processing (ACSP) |date=2015 |edition=1 |location=Heverlee, Belgium |publisher=Springer International Publishing AG Switzerland |publication-place=Cham, Switzerland |isbn=978-3-319-16135-8 |issn=1872-082X |doi=10.1007/978-3-319-16136-5 |lccn=2015935431}}
[3][4]
}}- System Interface Level 5 (SxI-5): Common Electrical Characteristics for 2.488 – 3.125 Gbit/s Parallel Interfaces. OIF, October 2002.
- TFI-5: TDM Fabric to Framer Interface Implementation Agreement. OIF, September 16, 2003
- Introduction to LVDS, PECL, and CML, Maxim, http://pdfserv.maxim-ic.com/en/an/AN291.pdf
- http://www.ee.iitm.ac.in/~nagendra/videolectures/doku.php?id=ee685:start
- Interfacing between LVPECL, VML, cml and LVDS Levels, http://focus.ti.com/lit/an/slla120/slla120.pdf
- For more details on design automation and low power design of CML circuits, see: http://lsm.epfl.ch
External links- JESD204B - a JEDEC Standard for serial data interfacing - Analog Devices
- JESD204B Overview (slides) - Texas Instruments
{{Logic Families}} 1 : Logic families |